Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10738 Date posted 04/23/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 5 -8 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You’ll Be Doing: - Designing, developing, and troubleshooting core algorithms for word-level synthesis. - Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. - Engaging in pure technical roles focused on software development and architecture. - Implementing multi-threaded and distributed code solutions. - Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. - Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: - Driving technological innovation in chip design and verification. - Enhancing the performance and quality of synthesis tools used globally. - Solving complex logic interference problems to improve design accuracy. - Contributing to the development of high-performance silicon chips and software content. - Collaborating with cross-functional teams to achieve project milestones. - Pioneering new software architectures that set industry standards. What You’ll Need: - Strong hands-on experience in C/C++ based software development. - Deep understanding of design patterns, data structures, algorithms, and programming concepts. - Familiarity with multi-threaded and distributed code development. - Knowledge of ASIC design flow and EDA tools and methodologies. - Proficiency in Verilog, SystemVerilog, and VHDL HDL. Who You Are: - Highly enthusiastic and energetic team player with excellent communication skills. - Strong desire to learn and explore new technologies. - Effective problem-solver with a keen analytical mind. - Experienced in working on Unix/Linux platforms. - Adept at using developer tools such as gdb and Valgrind. The Team You’ll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products. This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference. You will work closely with both local and global teams to drive technological advancements and achieve project goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Category Engineering Hire Type Employee Job ID 10481 Remote Eligible No Date Posted 13/04/2025 Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Participate in development of verification test plan, verification environment documentation and test environment usage documentation Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team and peers to accomplish all verification goals. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills. 5 + years of relevant experience At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 9672 Date posted 03/02/2025 Candidate will be part of VC PS Noida team. Design, develop, troubleshoot the core algorithms. Design and develop standard and customized features / checks in VC PS for inference, propagation and verification. Will be working with other local and global teams. Design and development of state of the art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the R&D team, you will contribute to Siemens’ success by crafting state of the art power analysis and optimization solutions. This is your role Analyzer team is working on the development of front end (Analyzer and Elaborator) of different Mentor Compilers. This module takes care of various HDL languages like Verilog, System Verilog and VHDL. As a member of the team, one will be working primarily on C++ and flex/bison and will be responsible for the design, development modify, and implementation of various pieces of the overall software with focus on surpassing customer expectations, on achieving high quality and timely delivery. Responsible for ensuring the overall functional quality of the released product on all required platforms and mechanism. Ability to understand complex products, solutions, and problems. Builds, documents, and executes software designs which may involve complicated workflows or multiple product areas. We are not looking for superheroes, just super minds We are seeking a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with significant experience in software development with 1-4 Years of experience. We value sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Experience in parallel algorithms, job distribution. Experience in development of Front End EDA software is a plus! Proficiency in HDL languages – Verilog/VHDL/System Verilog - low power aware synthesis and power formats - UPF/CPF – will supplemental. We are looking for knowledge of flex/bison and understanding of gate level digital logic design. Good analytical, abstraction and interpersonal skills will help in crafting bigger and balanced solutions for complex systems. Ability to work individually and as a team player will help in crafting good solutions and should be able to guide other towards project completion. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #LI-EDA #LI-HYBRID

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments Job description: PHY design Experienced analog/mixed-signal designer for high-speed PHYs design. It is mandatory that the candidate has in-depth understanding of analog and mixed-signal design, with hand-on design experience of PHY circuits. Specific areas of expertise/knowledge required: Voltage & current references, LDO regulator, high-accuracy comparator and amplifier High speed custom digital circuits like serializer, de-serializer, clock divider and synchronizer High Speed flops, gates operating at low voltage with best in class PPA Voltage and current mode transmitters, duty-cycle corrector TX/RX equalization techniques and circuits (e.g. CTLE, DFE) Calibration technique to tune for PVT variation Mixed mode simulation Transmission line theory, concept of PDN, device mismatch, system linearity and stability, low power design Following areas would be a significant Plus: Skills in scripting and automation Knowledge of common PHY protocols (DP, USB, Ethernet etc.) Concept of Quality in design and IP delivery Understanding of behavioral modeling of Analog circuits and RTL-to-GDS flow Skills Analog Mixed Signal ,PHY Circuit ,LDO regulator Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus), Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075441 Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: Years of experience 9+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC - SoC Design Verification Engineer) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 6+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering. Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member. You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification. You are a resourceful problem-solver, a team player, and have excellent communication skills. What You’ll Be Doing: Designing and developing emulation models. Implementing and verifying digital designs using System Verilog and Verilog. Developing scripts in Perl, TCL, or other languages. Collaborating with cross-functional teams. Conducting protocol verification for various standards. Utilizing UVM for design validation. The Impact You Will Have: Enhancing emulation model efficiency. Contributing to high-performance silicon chips. Improving design reliability through verification. Streamlining workflows with automation. Ensuring protocol compliance. Driving technological advancements. What You’ll Need: B.E / M.E. in Electronic & Communication / Computer Science Engineering. Proficiency in C/C++ and OOPS. Knowledge of digital design and HDL languages. Experience with scripting languages. Familiarity with multiple protocols like ethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHI and UVM. Who You Are: Effective communicator. Team player. Resourceful and detail-oriented. Innovative problem-solver. Adaptable learner. The Team You’ll Be A Part Of: Join a dynamic team dedicated to developing and verifying advanced emulation models for high-performance silicon chips. Collaborate with cross-functional teams to ensure seamless integration and adherence to industry standards. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details about the salary range and benefits during the hiring process. Inclusion and Diversity: Synopsys considers all applicants for employment without regard to race, color, religion, sex, gender preference, national origin, age, disability, or status as a Covered Veteran in accordance with federal law. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4 -10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a motivated and skilled engineer with 4-10 years of experience in emulation solutions development. You bring a strong foundation in programming concepts using C/C++ and an understanding of digital design. Your expertise includes HDL languages such as System Verilog and Verilog, and you are familiar with protocols like AXI, AMBA, JTAG, AVB, CAN, and TSN. You thrive in collaborative environments and have excellent communication skills. Your educational background includes a B.E/ B.Tech/ M.Tech in Electronic & Communication or Computer Science Engineering. You are passionate about developing cutting-edge emulation solutions for semiconductor customers and are eager to engage in both software development and synthesizable RTL development. What You’ll Be Doing: Developing emulation solutions for industry-standard protocols such as AXI, AMBA, JTAG, AVB, CAN, and TSN, CHI, Ethernet, PCIe, CXL, UCIe CSI, DSI, DP, UFS, MMC, HDMI, DRAM. Engaging in software development using C/C++ and synthesizable RTL development using Verilog. Verifying emulation solutions to ensure they meet the highest standards of quality and performance. Interacting with customers during the deployment and debugging phases to provide technical support and ensure successful implementation. Collaborating with cross-functional teams to integrate emulation solutions with other Synopsys products and technologies. Continuously improving and optimizing emulation solutions to meet evolving industry needs and standards. The Impact You Will Have: Enhancing the efficiency and performance of semiconductor design processes through advanced emulation solutions. Contributing to the development of high-performance silicon chips and software content that drive technological innovation. Supporting semiconductor customers in overcoming design and verification challenges, leading to successful product launches. Improving the reliability and functionality of emulation solutions, thereby increasing customer satisfaction and trust in Synopsys products. Driving continuous improvement and innovation within the emulation solutions domain. Facilitating seamless integration of emulation solutions with other Synopsys technologies, enhancing overall product offerings. What You’ll Need: Strong programming skills in C/C++ and understanding of OOPS concepts. Good understanding of digital design concepts. Knowledge of HDL languages such as System Verilog and Verilog. Experience with scripting languages like Perl or TCL is a plus. Understanding of ARM architecture is an added advantage. Knowledge of UVM and functional verification will be a plus. Who You Are: A team player with excellent communication skills. Detail-oriented and capable of working independently. Adaptable and eager to learn new technologies and methodologies. Proactive in identifying and solving problems. Passionate about delivering high-quality solutions. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing state-of-the-art emulation solutions for semiconductor customers. The team collaborates closely with other engineering groups within Synopsys to ensure seamless integration and optimal performance of our products. We value creativity, continuous learning, and a commitment to excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Experience : 4+ years Location: Chennai, Bangalore, Noida, Hyderabad, Cochin Responsibilities: Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL Perform functional verification using simulation and formal methods Participate in code reviews and ensure adherence to coding standards Analyze timing performance and perform static timing analysis (STA) Collaborate with design, verification, and synthesis teams to ensure successful tape-out Stay up-to-date with the latest RTL design methodologies and tools Show more Show less

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Description Candidate will be part of TCM Front End team. Design, develop, troubleshoot the core algorithms used in TCM Front End tool Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. Will be working with other local and global teams of TCM and VC SpyGlass Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. Create test cases to test the developed feature. Skills Required Strong knowledge of Front-end compilers and their flow Ability to develop new software architecture and good leadership skills. Fluent in C/C++ with extensive work experience in data-structures and algorithms. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Excellent algorithm analysis skills and a good knowledge of data structures. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Familiarity with multi-threaded and distributed code development. Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Quality focus - one who believes in quality and wants to make a difference. Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Location : Company Name: Mirafra Technologies Positionskill set : PCIE Experts (Design Verification) Location: Hyderabad Experience: 6 to 12 Years Open Positions: 8 Notice Period: 0 to 40 Days Preferred Job Type: Full-Time Selection Type: All offers are client selection-based Location: Hyderabad/Bangalore Job Description: Mirafra is hiring experienced PCIE Verification Engineers for exciting opportunities with leading semiconductor clients in Hyderabad. If you're passionate about solving complex verification challenges, we want to hear from you! Key Responsibilities: In-depth understanding of verification flows and methodologies Hands-on experience with complex testbenches/models in Verilog, SystemVerilog, or SystemC Strong debug skills and a problem-solving mindset Functional and SoC-level verification, including emulation exposure Proficiency in SystemVerilog, PLI/DPI interfaces, C/C++, Perl/Shell scripting , and assembly language Experience with OVM/UVM methodologies Ability to work collaboratively in a team environment Good communication and interpersonal skills Preferred Skills: Background in x86 or ARM architecture-based SoCs Experience in SoC/IP performance verification is a plus Apply Now: If you meet the above requirements and are available within 0 to 40 days, send your resume to: [swarnamanjari@mirafra.com] or Click the apply button

* Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# coding experience required This is a great opportunity to supplement your income while looking for longer or more full-time work, all while contributing to the development of new AI models using your domain expertise! Our client has hired over 1,000 Braintrust talent and intends to hire hundreds more! Many Braintrust coders earn over $12,000 per month! You’ll have the flexibility to work as much or as little as you choose - 20hrs/week is suggested, but not a limit. Start working in as little as 48 hours. Your final hourly rate will be chosen by Outlier AI and determined by your location. What to expect: If qualified, you’ll be invited to complete a brief questionnaire that takes 3-5 minutes. If you successfully pass the questionnaire, you’ll be approved and able to begin work ASAP. Required qualifications: Proficiency working one of the following languages: Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# Complete fluency in the English language is required. You should be able to describe code and abstract information in a clear way. Preferred qualifications: Bachelor's and/or Master's degree in Computer Science or equivalent. Students are welcome. Note : Outlier AI is partnering with Remotasks for this opportunity Show more Show less

* Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# coding experience required This is a great opportunity to supplement your income while looking for longer or more full-time work, all while contributing to the development of new AI models using your domain expertise! Our client has hired over 1,000 Braintrust talent and intends to hire hundreds more! Many Braintrust coders earn over $12,000 per month! You’ll have the flexibility to work as much or as little as you choose - 20hrs/week is suggested, but not a limit. Start working in as little as 48 hours. Your final hourly rate will be chosen by Outlier AI and determined by your location. What to expect: If qualified, you’ll be invited to complete a brief questionnaire that takes 3-5 minutes. If you successfully pass the questionnaire, you’ll be approved and able to begin work ASAP. Required qualifications: Proficiency working one of the following languages: Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# Complete fluency in the English language is required. You should be able to describe code and abstract information in a clear way. Preferred qualifications: Bachelor's and/or Master's degree in Computer Science or equivalent. Students are welcome. Note : Outlier AI is partnering with Remotasks for this opportunity Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER As a member of the AECG Product Validation and Solutions Teams within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. The Role At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen 6, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. Key Responsibilities Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans Pre-Silicon and Post Silicon validation for new PCIe enabled blocks Responsible for IP design, Silicon bring up, Validation and IP release Work in collaboration with the Global teams Preferred Experience Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog Proficient in RTL simulation tools (VCS, Modelsim) Knowledge of high-speed interfaces including, PCIe, CXL, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer Experience in developing system or IP prototypes using FPGAs Strong knowledge of IP/SOC design methodologies Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles Knowledge of C/C++ is an added advantage ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

* Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# coding experience required This is a great opportunity to supplement your income while looking for longer or more full-time work, all while contributing to the development of new AI models using your domain expertise! Our client has hired over 1,000 Braintrust talent and intends to hire hundreds more! Many Braintrust coders earn over $12,000 per month! You’ll have the flexibility to work as much or as little as you choose - 20hrs/week is suggested, but not a limit. Start working in as little as 48 hours. Your final hourly rate will be chosen by Outlier AI and determined by your location. What to expect: If qualified, you’ll be invited to complete a brief questionnaire that takes 3-5 minutes. If you successfully pass the questionnaire, you’ll be approved and able to begin work ASAP. Required qualifications: Proficiency working one of the following languages: Swift, Python, Java, Go, Verilog, Typescript, Javascript, C++, or C# Complete fluency in the English language is required. You should be able to describe code and abstract information in a clear way. Preferred qualifications: Bachelor's and/or Master's degree in Computer Science or equivalent. Students are welcome. Note : Outlier AI is partnering with Remotasks for this opportunity Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 2+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability. Role Responsibility Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical of experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149.1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We’re doing work that matters. Help us solve what others can’t. Show more Show less

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the R&D team, you will contribute to Siemens’ success by crafting state of the art power analysis and optimization solutions. This is your role Analyzer team is working on the development of front end (Analyzer and Elaborator) of different Mentor Compilers. This module takes care of various HDL languages like Verilog, System Verilog and VHDL. As a member of the team, one will be working primarily on C++ and flex/bison and will be responsible for the design, development modify, and implementation of various pieces of the overall software with focus on surpassing customer expectations, on achieving high quality and timely delivery. Responsible for ensuring the overall functional quality of the released product on all required platforms and mechanism. Ability to understand complex products, solutions, and problems. Builds, documents, and executes software designs which may involve complicated workflows or multiple product areas. We are not looking for superheroes, just super minds We are seeking a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with significant experience in software development with 1-4 Years of experience. We value sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Experience in parallel algorithms, job distribution. Experience in development of Front End EDA software is a plus! Proficiency in HDL languages – Verilog/VHDL/System Verilog - low power aware synthesis and power formats - UPF/CPF – will supplemental. We are looking for knowledge of flex/bison and understanding of gate level digital logic design. Good analytical, abstraction and interpersonal skills will help in crafting bigger and balanced solutions for complex systems. Ability to work individually and as a team player will help in crafting good solutions and should be able to guide other towards project completion. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced virtual interface solutions such as Accelerated Verification IP’s and Virtual Bridges solutions for Cadence’s hardware emulation and prototyping platforms. Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 8+ years industry experience We’re doing work that matters. Help us solve what others can’t. Show more Show less

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X) . Principal Engineer, Design Verification The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI. We’re seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components, subsystems from scratch. About the role In this position the successful candidate will be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career. Responsibilities Verification of complex Digital designs and sub-systems using leading edge verification methodologies. Architecting a unified verification testbench environment Defining verification strategy, testplans, tests and verification methodology for chip-level verification. Working with the design team in generating test-plans and closure of code and functional coverage Technically mentoring verification engineers on SoC Verification responsible for block/IP-level DV Continuous interaction with Design, Architecture and Firmware teams Tracking and management of design verification improvements Required Qualifications Bachelor's or Master’s degree, in Engineering (Electronic Engineering) or equivalent. 15 years ASIC design verification or related work experience. Leadership skills enabling one to define and implement a verification strategy Demonstrated ability to communicate with peers, managers, and project stakeholders effectively using both verbal and written communications Proficient in developing unit and SoC level test benches using UVM Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology, formal verification Behavioral modeling of analog blocks, System Verilog Real-Number Modeling, behavioral model validation and mixed-signal simulators like Cadence Xcelium Working with processors Gate Level Simulation (GLS) verification flow for SoC verification. Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting Experience in Property Specification Language (PSL), Matlab (including for co-simulation and HDL generation) and digital signal processing would be a plus Low power methodologies such as CPF/UPF Excellent interpersonal and communication skills and the dream to take on diverse challenges Self-motivated and enthusiastic For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days