2315 Verilog Jobs - Page 25

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER T HE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. P REFERRED EXPERIENCE : Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Job description Company: ARF Design Pvt Ltd Location: Bhubaneswar and Ranchi Employment Type: Full-Time | Permanent Working Days: Monday to Saturday Interview Mode: Face-to-Face Job Description:– Analog Layout Engineer We are actively hiring Analog Layout Engineers with 3+ years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: ● 3+ yrs of relevant Analog Layout experience ● Proficiency in LVS/DRC checks and EDA tools ● Experience with lower technology nodes (3nm,5nm,7nm,10, 16nm / 28nm ETC) ● Good understanding of layout matching, parasitic extraction, and floor planning ● Strong verbal and written communication skills ● Ability to work independently and within cross-functional teams Job Description:– Circuit Design Engineer ARF Design is hiring Analog Mixed Signal Designers to work on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Key Responsibilities: ● Derive circuit block level specifications from top level specifications ● Perform optimized transistor-level design of analog and custom digital blocks ● Run SPICE simulations to meet detailed specifications ● Guide layout design for best performance, matching, and power delivery ● Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) ● Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits ● Conduct design reviews at various phases/maturity of the design Qualifications: ● BE/M-Tech in Electrical & Electronics ● Strong fundamentals in RLC circuits, CMOS devices and digital design concepts (e.g., counters, FSMs) ● Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators ● Collaborative mindset with a positive attitude Exp: 3+ Please share updated resume [Name_Post_Exp] to divyas@arf-desgn.com Job Types: Full-time, Permanent Work Location: In person

Greetings from the Department of Electronics and Communication Engineering, NIT Rourkela. We are pleased to invite applications for the post of Research Fellow (RF) and Project Associates (PA) under a prestigious research project funded by the Department of Telecommunications (DOT), Government of India, titled: 🎯 “Waveform Design, Testing, and Verification for Joint Radar and Communication at Millimeter Wave Frequency Band.” 📌 Key Details: Number of Positions: 03 (RF 1 position, PA 2 position) Duration: Up to December 2027 Monthly Fellowship: ₹45,000/- for RF, ₹22,500/- for PA Mode of Interview: Online Interview Date: August 13, 2025, 10:00 AM Last Date to Apply: August 11, 2025 Department: Electronics and Communication Engineering, NIT Rourkela 🎓 Eligibility Criteria RF: M.Tech/M.E/MS or equivalent in ECE, EE, CSE, RF, Microwave, Telecommunication, Signal processing, AI/ML, VLSI, etc. Or M.Sc./MCA Or B.Tech/B.E with GATE score for RF 🎓 Eligibility Criteria PA: B.Tech/B.E in ECE, EE, CSE, MSc Minimum 60% marks or 6.5/10 CGPA throughout Responsibilities: RF: Conduct research on development of joint radar and communication (JRC) technology. Designing, simulating, and testing of waveform for JRC. Design, validate the concept in SDR/ FPGA module. PA: Develop conceptual hardware to prove JRC concepts. Design and development of millimetre wave hardware for 6G wireless communication as well as radar functionality. Testing and debugging RF and baseband circuits. 🧠 Desired Skills: Strong knowledge at least in two research areas among the following: 1) digital signal processing. 2) Embedded Systems. 3) wireless communication. 4)Antenna Design, 5) RF circuit design, debugging, and testing. Programming proficiency in Python, MATLAB, VHDL/Verilog, etc. Exposure to hardware (SDR, FPGA, RF-Soc) and EDA tools preferred This opportunity also opens avenues for M Tech Research/ Ph.D. admission, subject to eligibility and institute norms. Interested candidates may reach out to the PI: Prof. Subrata Maiti 📧 Email: smaiti@nitrkl.ac.in Advertisement Details can be found in NIT Rourkela website: https://nitrkl.ac.in/SRICCE/Career

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience - Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable - Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Able to lead IP/Sub-System/Soc Team as Overall Project Functional Lead (PFL) Study industry standard methodologies and quickly implement same in the team Develop test plans, tests and verification infrastructure for complex IP/sub-system/SOC Expertise in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Expertise in SVA development like coding, porting and maintaining System Verilog Assertions and Formal Verification Guide junior members , lead projects and manage global stakeholders Define state of the art Logic Verification methodology and participate in innovation and initiatives Development of tools for Design and Verification support. Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 13+ Years of the relevant work experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations, RNM Verification Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal, vManager Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Design Verification Engineer (5+ years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement

Embedded Domain RTL/FPGA Design Engineer(Fresher) Min 0 - 3 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. Apply Now Related Job Openings Embedded Domain Embedded Software Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain Embedded Software Engineer(Fresher) Min 0 - 3 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details

Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. Apply Now Related Job Openings Embedded Domain Embedded Software Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain Embedded Software Engineer(Fresher) Min 0 - 3 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details

RTL Design Engineer (5+ years’ experience) Company: HCL Tech Job Summary: We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation ASICs/SoCs. You will be responsible for all aspects of RTL design, from concept to RTL coding, verification, and integration. Responsibilities: Develop RTL code for complex digital circuits using Hardware Description Languages (HDLs) such as Verilog or VHDL Perform functional verification using simulation and formal methods Participate in code reviews and ensure adherence to coding standards Analyze timing performance and perform static timing analysis (STA) Collaborate with design, verification, and synthesis teams to ensure successful tape-out Stay up-to-date with the latest RTL design methodologies and tools Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5+ years of experience in RTL design for ASICs/SoCs Proven experience in designing and verifying complex digital circuits Proficiency in Verilog or VHDL Experience with verification methodologies (e.g., UVM) Strong understanding of digital design concepts (combinational logic, sequential logic, state machines) Experience with SDC (Standard Delay Constraint) format for timing closure Experience with scripting languages (e.g., Python, Perl) is a plus Excellent communication, teamwork, and problem-solving skills Benefits: Competitive salary and benefits package Opportunity to work on cutting-edge technologies Collaborative and fast-paced work environment Potential for professional growth and development

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER Lead ASIC Security Design Verification Engineer Position Overview We are seeking a Lead ASIC Security Design Verification Engineer to drive verification strategy and lead a team of engineers. The role involves architecting verification environments, mentoring team members, and ensuring robust security implementations in complex ASIC designs. Essential Responsibilities Lead and manage a team of design verification engineers Define and drive verification methodology and strategy for security-focused ASIC projects Architect advanced verification environments using UVM methodology Review and approve verification plans, test scenarios, and coverage metrics Guide technical decisions for verification infrastructure and framework development Establish best practices for security verification across projects Drive cross-functional collaboration with design, software, and product teams Provide technical leadership in verification reviews and project meetings Mentor and develop team members' technical and professional growth Required Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field 10+ years of Hardware Engineering experience with at least 5 years in lead verification roles Proven track record of leading complex verification projects and teams Expert-level knowledge in RTL design verification using Verilog/System Verilog/UVM methodology In-depth understanding of security protocols and cryptographic implementations: Symmetric and asymmetric cryptography Public/private key infrastructure Hash functions and random number generators Encryption/signature algorithms (AES, SHA, GMAC) Inline cryptography Advanced programming skills in Verilog, C/C++, Python, and Perl Strong experience in verification planning and coverage-driven verification Exceptional problem-solving and debugging skills Outstanding leadership and communication abilities Preferred Qualifications Master's degree in Electrical Engineering Experience leading security-critical tape-outs Expertise in hardware security architecture and threat modeling Knowledge of formal verification methodologies Experience with verification IP development and reuse strategies Track record of implementing verification process improvements Publications or patents in hardware security or verification Leadership Competencies Proven ability to build and lead high-performing technical teams Excellence in project planning and execution Strong decision-making and problem-solving abilities Effective stakeholder management skills Ability to mentor and develop team members Strategic thinking and innovation mindset Technical Leadership Establish verification standards and methodologies Drive adoption of new verification technologies and tools Lead technical reviews and design discussions Guide architectural decisions for verification environments Contribute to organizational verification strategy Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver quality RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Company: ARF Design Pvt Ltd Location: Bhubaneswar and Ranchi Employment Type: Full-Time | Permanent Working Days: Monday to Saturday Interview Mode: Face-to-Face Job Description:– Analog Layout Engineer We are actively hiring Analog Layout Engineers with 3+ years of industry experience. Ideal candidates must have solid expertise in lower technology nodes, physical layout techniques, and verification processes. ARF provides an excellent platform to work on advanced nodes with fast-track interview and onboarding processes. Key Responsibilities: ● Design and development of analog layout IP blocks and full-chip integration ● Perform and resolve LVS/DRC violations independently ● Collaborate with circuit design teams to optimize layout quality and performance ● Ensure layouts meet design matching and parasitic constraints ● Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: ● 3+ yrs of relevant Analog Layout experience ● Proficiency in LVS/DRC checks and EDA tools ● Experience with lower technology nodes (3nm,5nm,7nm,10, 16nm / 28nm ETC) ● Good understanding of layout matching, parasitic extraction, and floor planning ● Strong verbal and written communication skills ● Ability to work independently and within cross-functional teams Job Description:– Circuit Design Engineer ARF Design is hiring Analog Mixed Signal Designers to work on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Key Responsibilities: ● Derive circuit block level specifications from top level specifications ● Perform optimized transistor-level design of analog and custom digital blocks ● Run SPICE simulations to meet detailed specifications ● Guide layout design for best performance, matching, and power delivery ● Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) ● Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits ● Conduct design reviews at various phases/maturity of the design Qualifications: ● BE/M-Tech in Electrical & Electronics ● Strong fundamentals in RLC circuits, CMOS devices and digital design concepts (e.g., counters, FSMs) ● Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators ● Collaborative mindset with a positive attitude Exp: 3+ Please share updated resume [Name_Post_Exp] to divyas@arf-desgn.com

Role Description We are looking for an experienced and passionate Design and Verification Trainer to train and mentor aspiring engineers in RTL design , functional verification , and VLSI concepts . The ideal candidate should have hands-on experience with front-end design and verification methodologies and be comfortable delivering technical content in a structured, engaging, and clear manner. Required Skillsets Strong knowledge of hardware description languages like Verilog/System Verilog Proficiency in verification methodologies such as Universal Verification Methodology (UVM)/ SystemVerilog Assertions (SVA) is crucial Experience with simulation and debugging tools (e.g. Synopsys VCS/VERDI, Spyglass) Proficiency in Scripting Analytical and Problem Solving Skills Qualifications Master's degree in Electronics/VLSI Design (Preferable) Curriculum Development expertise Teaching and Instructional Design abilities Training experience Excellent communication and presentation skills Experience in VLSI design or semiconductor industry Design Thinking skills

As a Silicon Design Validation Engineer at Lattice, you will have the opportunity to work on cutting-edge projects within the Silicon Engineering team. Your primary responsibility will involve validating building blocks in FPGA on board level to ensure functionality and performance align with the design intent. This will include various IPs such as SERDES (PMA/PCS), Memory DDR (DDR4, LPDDR4, DDR5, etc.), DPHY, PLL, DSP, Fabric, and I/O components. In this role, you will develop validation and characterization plans for specific IPs, bench hardware, and software. You will also be responsible for creating test logic RTL to execute validation and characterization tests effectively. Additionally, you will play a key role in driving new silicon product bring-up, validation, and debugging processes to assess IP functionality and performance, ultimately contributing to data sheet preparation. You will collaborate closely with design, verification, manufacturing, test, quality, and marketing teams throughout the product lifecycle, from Silicon arrival to product release. Furthermore, you will provide support to address customer issues post-product release, demonstrating strong written and verbal communication skills and the ability to work effectively in a cross-functional environment. The ideal candidate for this role should possess an Electrical Engineering degree with a strong passion for pursuing a career in Silicon Design Validation. You should have at least 2 years of experience and a solid understanding of High-Speed Serdes Interface characterization, including protocol compliance testing for interfaces like PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, MIPI CSI/DSI-2, USB, DisplayPort, and HDMI. Moreover, you should have knowledge in high-speed board design, signal integrity evaluation/debugging, Verilog/VHDL, FPGA development tools, and test automation using programming languages like Python and Perl. Familiarity with statistical analysis concepts, tools such as JMP and R, and bench equipment for device characterization will be beneficial. If you are a self-motivated individual with strong problem-solving and critical thinking skills, eager to work in a collaborative and challenging environment, then this role at Lattice may be the perfect opportunity for you to grow and excel in the field of Silicon Design Validation Engineering.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. This includes a wide range of tasks such as bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To qualify for this role, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. In this position, you will have the opportunity to closely interact with the product definition and architecture team, develop implementation strategies to meet quality and performance goals for the Sub-system, and define various aspects of block-level design. Your responsibilities will also include leading a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug, driving Lint/CDC/FV/UPF checks to ensure design quality, and developing Assertions as part of white-box testing-coverage. You will work with stakeholders to discuss collateral quality, identify solutions/workarounds, and deliver key design collaterals like timing constraints and UPF. Desired skills for this role include a good understanding of low power microarchitecture techniques and AI/ML systems, thorough knowledge of Computer system architecture, experience in high-performance design techniques, and trade-offs in Computer microarchitecture. You should also be knowledgeable in NoC Design principles, define Performance and Bus transactions based on use cases, work with Power and Synthesis teams, have expertise in Verilog/System Verilog, and experience with simulators and waveform debugging tools. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those concerning the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to use this site. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, please contact Qualcomm Careers directly.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today's AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software, and systems to deliver solutions that improve AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI's solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems. We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities include Packet Processing Design, Implementation and Testing, Performance Optimization, Protocol Support, and Troubleshooting and Debugging. The ideal candidate should have ME/BE with a minimum of 8-15 years of experience, working knowledge of system Verilog and Verilog, proven expertise in designing and optimizing packet pipelining and QoS mechanisms for high-speed networking devices, solid understanding of ASIC design methodologies, experience with Ethernet/PCIe networking protocols, strong analytical and problem-solving abilities, as well as excellent verbal and written communication skills. At Eridu AI, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.,

Job Details Job Description: Do Something Wonderful - Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? The Intel Bengaluru office is dedicated to designing SerDes IP for use by customers that require flexible protocol support in addition to best-in-class performance and power. We have a long track record of silicon success over multiple technology nodes. We are looking for a Firmware engineer to help develop next-generation high-speed SerDes IP. If you're ready to be a part of this journey, then we want to hear from you. As a Firmware Engineer, you will - Perform software design implementation for custom IP- Conduct code reviews to improve software design and ensure code quality.- Analyze results and makes recommendations to improve code performance for current and future product architecture.- Optimize design to improve product level parameters such as memory utilization and power consumption. Participate in the development and improvement of software design methodologies and test automation. Qualifications Qualifications:You must possess the below minimum qualifications to be initially considered for this position and preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates: Minimum Qualifications:- The candidate must have a Bachelor's degree in Electrical or Computer Engineering or equivalent and 3+ years of experience OR a Master's degree in Electrical or Computer Engineering or equivalent and 1+ years of experience. Experience must include:- Deep understanding of the Software design cycle- Knowledge of Bare Metal or RTOS Firmware implementation.- Using C/C++ tools: GCC and/or LVVM Clang Compiler, GNU and JTAG Debuggers.- Scripting skills in Python and Shell programming- Git revision control software- Knowledge of software build methods using a makefile and CMake- Strong analytical, problem solving, and communication skills with the ability to independently draw conclusions Preferred Qualifications:- Experience with development or customization of flows.- Understanding of Verilog /SystemVerilog simulation for Firmware Co-simulation- Ability to work through technology challenges and issues associated with high-performance design implementations. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5

Sr. Staff RTL Design Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10862 Remote Eligible No Date Posted 13/07/2025 Job Titles: Senior Staff ASIC RTL Design Engineer - Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design. You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products. With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL. Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA.You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools. You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues. Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores. You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery.You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project. If you re ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family. Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks. Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development. Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation. Interacting with customers to understand and refine specification requirements and providing technical guidance as needed. Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team. Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies. The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide. Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers. Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise. Enhancing team performance through mentorship, knowledge sharing, and technical guidance. Strengthening Synopsys reputation as a leader in chip design by consistently delivering on complex customer requirements. Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies. What You ll Need: Bachelor s or Master s degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design. Expertise in data path and algorithmic block design (e.g., Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs. Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools. Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking. Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2). Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus. Familiarity with revision control systems (e.g., Perforce) and scripting languages (Perl/Shell). Prior experience as a technical lead or mentor within a design team is highly desirable. Who You Are: A collaborative team player who thrives in a global, distributed environment. An effective communicator, adept at conveying complex technical ideas to diverse stakeholders. A proactive problem-solver with strong analytical skills and high initiative. Detail-oriented, quality-focused, and committed to delivering excellence. Passionate about mentoring and enabling the growth of others. Dedicated to diversity, inclusion, and fostering an open, respectful workplace. The Team You ll Be A Part Of: You ll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry. The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications. Working in a multi-site, global environment, you ll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Staff Processor Verification Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You ll Need: Bachelor s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Description Job Title: Sr. Engineer, Hardware Verification Job Location: Bangalore, India Job ID: AI2413 Job Description: As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ai s MLSoC . You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team. Minimum Qualifications: BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Preferred Qualifications: ML experience C/C++ Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.