2321 Verilog Jobs - Page 26

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5

Sr. Staff RTL Design Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10862 Remote Eligible No Date Posted 13/07/2025 Job Titles: Senior Staff ASIC RTL Design Engineer - Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design. You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products. With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL. Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA.You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools. You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues. Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores. You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery.You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project. If you re ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family. Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks. Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development. Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation. Interacting with customers to understand and refine specification requirements and providing technical guidance as needed. Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team. Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies. The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide. Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers. Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise. Enhancing team performance through mentorship, knowledge sharing, and technical guidance. Strengthening Synopsys reputation as a leader in chip design by consistently delivering on complex customer requirements. Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies. What You ll Need: Bachelor s or Master s degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design. Expertise in data path and algorithmic block design (e.g., Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs. Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools. Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking. Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2). Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus. Familiarity with revision control systems (e.g., Perforce) and scripting languages (Perl/Shell). Prior experience as a technical lead or mentor within a design team is highly desirable. Who You Are: A collaborative team player who thrives in a global, distributed environment. An effective communicator, adept at conveying complex technical ideas to diverse stakeholders. A proactive problem-solver with strong analytical skills and high initiative. Detail-oriented, quality-focused, and committed to delivering excellence. Passionate about mentoring and enabling the growth of others. Dedicated to diversity, inclusion, and fostering an open, respectful workplace. The Team You ll Be A Part Of: You ll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry. The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications. Working in a multi-site, global environment, you ll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Staff Processor Verification Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You ll Need: Bachelor s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Description Job Title: Sr. Engineer, Hardware Verification Job Location: Bangalore, India Job ID: AI2413 Job Description: As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ai s MLSoC . You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team. Minimum Qualifications: BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Preferred Qualifications: ML experience C/C++ Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

Job Title: Sr. Engineer, Hardware Verification Job Location: Bangalore, India Job ID: AI2413 Job Description: As the Hardware Design Verification Engineer, you will develop the verification methodology for SiMa.ai s MLSoC . You will be responsible for developing test plans, testbenches, drivers, monitors and checkers/scoreboard, testcases, coverage analysis and simulation, verify the functionality, performance and other aspects of RTL designs including the block-level and chip/system level, emulation and validation support. You will work very closely with the Architecture, RTL/uArch, and cross-functional teams. Areas of focus: Verification Methodology, Testbenches, drivers, checkers, test plans. Support for emulation, simulators, chip validation. Active interaction with RTL/uArch team. Minimum Qualifications: BS in Computer Science/EE with 4+ years of experience or MS in Computer Science/EE with 2+ years of experience in HW Design Verification. Experience with block level, cluster level or chip/SoC level verification. Proficiency in UVM methodology, Constrained Random, Coverage Driven Methodology, Verilog, SystemVerilog. Expertise in scripting languages, python or perl. Strong experience in helping emulation and validation. Experience with modeling various HW blocks, IPs for verification, emulation. Ability to analyze systems-level performance, profiling, and analysis. Preferred Qualifications: ML experience C/C++ Personal attributes: Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.

About the Company: Founded with the vision of building a runtime reconfigurable, future-proof processor, Morphing Machines is a fabless semiconductor company working on a ground-breaking technology that will transform the chip design landscape. Morphing Machines patent protected IP, REDEFINE, can concurrently accelerate heterogenous workloads, on a homogenous fabric of processing cores. REDEFINE combines ASIC (Application Specific Integrated Circuit) like performance with the reconfigurability of FPGAs (Field Programmable Gate Arrays). Morphing Machines innovation enables dataflow compute, which is a paradigm shift in the current processor industry. Due to the nature of our architecture, we can cater across domains from Data Centers, Quantitative Finance, AI/ML acceleration, Edge Vision to High Performance Compute (HPC) applications, all with the same hardware fabric. At Morphing Machines, we are building a cutting-edge technology guided by our vision to build truly software-defined hardware. Role Overview: As the Senior FPGA Engineer, you will play a mission-critical role in integrating FPGA designs on both cloud-hosted (AWS F1/F2) and on-premise FPGA platforms. You will own the entire lifecycle of FPGA bring-up, from IP handoff and integration to multi-fabric orchestration and performance validation. You will work closely with product, compiler, and orchestration teams to ensure FPGA-resident applications can be easily deployed, monitored, and benchmarked. Your responsibilities will include validating bitstreams, implementing communication pipelines, and enabling test/demo infrastructure across compute fabrics implemented over various FPGA s. Key Responsibilities: FPGA Bring-Up & Bitstream Integration Interface with the IP team to integrate design drops into deployable bitstreams. Bring up bitstreams on AWS F1/F2 instances, Xilinx VCU platforms, or other compatible boards. Debug issues related to I/O wrapper logic, timing, etc. Platform and Tooling Integration Work with Switchboard and FireSim environments to support application execution across multiple FPGA boards. Contribute to building a Continuous Integration/Deployment (CI/CD)-like pipeline for FPGA validation and test deployment. Establish protocols to bring up and manage multi-FPGA topologies. Application Enablement and Profiling Support application developers in deploying and profiling workloads coded in C with Hardware specific pragmas on FPGA targets. Validate compute vs communication tradeoffs; capture latency, throughput, and power KPIs. Enable applications such as voxel pooling, BFS, and encrypted inference. Documentation and Enablement Document the end-to-end FPGA bring-up workflow, including toolchains, setup guides, debug logs, and issue trackers. Required Skills and Qualifications: Technical Skills: Strong experience with Xilinx toolchains (Vivado, Vitis) , FPGA flows and implementation of design across FPGA boards Hands-on exposure to cloud-based FPGA platforms such as AWS F1/F2 Solid understanding of RTL development using Verilog/SystemVerilog Familiarity with memory controllers, timing analysis, and interface protocols Tooling & Workflow Integration: Experience with FPGA integration in CI/CD environments Knowledge of simulation and emulation frameworks Understanding of software-hardware co-design and ability to assist with application bring-up (C/C++) Soft Skills: Strong debugging and problem-solving skills Comfortable working in fast-paced, ambiguous environments Excellent communication and collaboration skills Ability to take ownership of integration across multiple teams Education and Experience: Bachelor s or Master s degree in Electronics, Electrical, or Computer Engineering 10+ years experience in FPGA bring-up, hardware integration, or system-level FPGA projects Preferred Skills (Bonus): Experience with Switchboard, FireSim, or multi-fabric orchestration Familiarity with compiler-level hardware mapping Understanding of OpenCL, LLVM, or machine-generated IR flows Ability to assist in building test infrastructure for cloud FPGA CI/CD Apply Now

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

About Cranes Varsity : Cranes Varsity is a pioneer Technical Training institute turned EdTech Platform offering Technology educational services for over 24 years. Being a trusted partner of over 5000+ reputed Academia, Corporate & Defence Organizations we have successfully trained 1 Lakh+ engineers and placed 70,000+ engineers. Cranes Varsity offers high-impact hands-on technology training to Graduates, Universities, Working Professionals, and the Corporate & Defence sectors. Job Title: Technical Trainer (Faculty) - C, C++ Position Technical Trainer (Faculty) - C, C++ Department Technical Training (Hardware) Experience Minimum 3 Years - 8 Years of EdTech / IT / Corporate / Institutions etc Education - Should have completed Any Degree BE, BTECH, ME, MTECH, MCA Job Description Strong Training experience highly preferred in Embedded C, C++, Data Structures, OOPS Concepts, Python. Hands on programming with C, C++, Verilog, Linux operating systems, Shell scripting, ARM, MATLAB, Embedded system software etc. Expertise in handling multiple inhouse and corporate trainings with proven track record and quality delivery. Experienced in course content development based on the training requirements. Course material development Experience in developing Hands-on projects and hand-holding large groups of students in the same. Experienced in all phases of product life cycle including requirements, design, coding Managing all aspects of the training cycle i.e. Training need analysis, course development, implementation and delivery, monitoring and evaluation. Ensuring quality delivery to students Establish expectations with project members and provide timely feedback Manage the work of developer resources, mentoring and coaching as needed Provide programming direction to a team of trainers Roles & Responsibilities Training Graduate Engineers, Working professionals, Corporates, freshers & Laterals. College Workshop Trainings. Content Development, Technical Assessment and Evaluation, Project development. Desired Skills and Experience Negotiation Skills Selling to Customer Ne edsMotivation for Sales & Target Oriented Building Relationships Desired Candidate Profile Excellent communication skills written and verbal and negotiation skills Knowledge of functioning of academic institutions and placement process The candidate should have good interpersonal skills and networking in the market. Minimum 3 years of Technical Training/Teaching experience preferred Multi-tier architecture knowledge Excellent self-management skills (task lists, status reports, prioritisation) Commitment to quality and timely deliverable Desire to understand the business For

RHEL Admin Certified Basic Infra Knowledge: VM, Network, Storage VMWare Console experience to setup and configure VMs PostgreSQL Cluster administration Bash and Shell script Able to do network troubleshooting RHEL hardening Experience Good to have Openshfit or Kubernetes 2-3 years CICD/Jenkins 3 years Ansible 1-2 years Security knowledge

Develop knowledge on protocols and products based on industry leading protocols such as I3C, DDR, SD, AXI, AHB Gain knowledge on ASIC flow and learn various tools used in the ASIC flow Work with a team of highly experienced applications engineers to provide comprehensive consulting on our IP products Participate in providing feedback on product documentation and collateral Develop presentation and team working skills What you'll Need: Currently pursuing a masters degree in Electrical/Electronic/Computer Engineering with exposure to VLSI, Verilog, coding skills, FPGAs A self-motivated and excellent communicator will be ideal candidate for this role

Job Title:DEVOPS- AWS Glue, KMS, ALB , ECS and Terraform/TerragruntExperience5-10YearsLocation:Bangalore : DEVOPS, AWS, Glue, KMS, ALB , ECS, Terraform, Terragrunt

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Required Skills and Experience : Bachelor’s or Master’s Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs : Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis. Must have experience with Siemens, Synopsys and/or Cadence Cad tools. Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python. Responsibilities - Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level. Generate and validate ATPG patterns using simulations. Shall Validate the DFT implementation using RTL and Gate level simulation. Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation. Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program. Chip in to the overall DFT methodology development. Nice to have Skills/Experience :- Shall have Knowledge of IEEE 1149.6, 1500 and 1838. Good experience on Hierarchical Scan implementations with core wrapping concepts Experience in handling multi-clock domains and low power design implementation. Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation. Communicate effusively with multi-functional functional teams in different geographies and time Zones. Time management and multi-tasking skills. Job Location: You will be joining part of growing team in Hyderabad About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you—you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You’ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

DFT SMTS Silicon Design Engineer New Dehli, India Engineering 66818 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER T HE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. P REFERRED EXPERIENCE : Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

To play a pivotal role in designing and implementing complex technical solutions, ensuring they align with business objectives and industry best practices. (1.) Key Responsibilities 1. To design and architect large-scale solutions, ensuring scalability, performance, and security. 2. To train and develop team so as to ensure that there is an adequate supply of trained manpower in the said technology and delivery risks are mitigated. 3. To continuously upskill with cutting-edge tech to deliver high-quality, future-proof solutions meeting client expectations and industry standards. 4. To leverage domain/tech expertise to gather client needs, deliver solutions, and craft a technology strategy aligned with business goals. No. of Positions 4 Skill (Primary) Technical Skills (ERS)-VLSI-Technology-SoC Auto req ID 1555973BR Skill Level 3 (Secondary Skill 1) Technical Skills (ERS)-VLSI-Verification Methodology-UVM Skill Level 3 (Secondary Skill 2) Technical Skills (ERS)-VLSI-RTL Coding Languages-Verilog Skill Level 3 (Secondary Skill 3) Technical Skills (ERS)-Languages-C++

To oversee multiple design teams, set organizational design standards, and drive innovation in the design process and ensure that design efforts have a significant impact on achieving business objectives. (1.) Key Responsibilities 1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences. 2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals. 3. To present design concepts and play a crucial role in shaping the overall design vision and strategy. 4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design. No. of Positions 8 Skill (Primary) Technical Skills (ERS)-VLSI-Technology-SoC Auto req ID 1555972BR Skill Level 3 (Secondary Skill 1) Technical Skills (ERS)-VLSI-Verification Methodology-UVM Skill Level 3 (Secondary Skill 2) Technical Skills (ERS)-VLSI-RTL Coding Languages-Verilog Skill Level 3 (Secondary Skill 3) Technical Skills (ERS)-Languages-C++

Dear connections We are hiring RTL Design Engineer Experience: 5+years Location: Bangalore JOB DESCRIPTION RTL coding knowledge Top-level (SOC) level basic industry standard Arch knowledge SoC & IP level Integration knowledge IPXACT knowledge IORING and Phys & GPIOs basic functionality Design Partitioning(Tilification) knowledge Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge Tools knowledge: VC static or equivalent other tools (VSI) VC_spyglass LINT, CDC and RDC 0in Formality and conformal LEC tool Design and scripting languages: Verilog and SV Perl Python TCL If you are interested, please share your resume to yasodha.balan@semi-leaf.com

Job Title: VLSI Engineer (Academic Role – Teaching Computer Architecture) Location: Rishihood University, Sonipat (On-site) Type: Full-Time | Immediate Joiners Preferred Experience: 3–7 years Department: Engineering & Technology | Academic Instruction About the Role: We are looking for VLSI engineers with a strong foundation in digital systems and computer architecture to take on an academic teaching role. This full-time position is ideal for engineers with hands-on experience in RTL design, processor components, or SoC architecture who are excited to teach how computers are built—from logic gates to microarchitectures. You will lead classroom instruction, mentor student projects, and help shape curriculum at the intersection of digital logic, hardware systems, and architectural design. Key Responsibilities: Teach Computer Architecture by drawing from real-world VLSI design experience—covering instruction sets, pipelining, memory systems, and microprocessor implementation. Guide students through lab simulations and RTL projects that explore how architectural concepts are implemented in hardware (e.g., datapaths, control units, cache design). Design and evaluate lab work, assessments, and hands-on student projects that simulate industry applications. Mentor and support students in their academic and professional development journeys. Continuously update course content to reflect current industry trends and technologies. Collaborate with fellow faculty, industry mentors, and curriculum designers to enrich learning outcomes. Contribute to curriculum development, academic research, and internal learning initiatives. Host technical workshops, design challenges, and guest sessions to extend classroom learning. Must-Have Skills & Qualifications: B.Tech / M.Tech / Ph.D. in Computer Engineering , Electronics , Electrical , or a related field. Experience working on processor subsystems, SoC integration, RTL for custom compute blocks, or related architecture-level VLSI work. Strong technical command over topics such as: Computer Architecture: Instruction sets, microprocessors, memory hierarchy, pipelining, cache systems. VLSI Design: CMOS circuits, RTL design, ASIC/FPGA flow, timing analysis, layout. Proficiency in tools such as Cadence , ModelSim , Synopsys , Xilinx , Mentor Graphics , etc. Working knowledge of HDL languages (Verilog/VHDL) and scripting ( Tcl , Shell , Python ). Excellent communication and classroom delivery skills. Demonstrated interest in teaching and mentoring students. Good-to-Have Skills: Prior experience as a faculty member or technical trainer. Familiarity with RISC-V , ARM-based processors, SoC Design, or low-power systems. Exposure to DFT , verification methodologies, and EDA flows. Contributions to open-source, academic publications, or online technical content. Comfort with digital tools, LMS platforms, and collaborative teaching formats. Why Join Us? Work at the intersection of deep tech and academia in a modern, innovation-led learning environment. Influence curriculum and pedagogy at a forward-thinking institution backed by Newton School of Technology and Rishihood University . Collaborate with a team of industry leaders and passionate educators in building India’s next generation of engineers.

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

12+ years of experience with a Bachelors'/ Master's degree in the field of Electrical, Electronics, or computer engineering Should have a good understanding of verification flow, challenges, and requirements of functional verification. Have worked on IP level or Block level or SoC level functional verification. Experience with digital verification aspects such as constrained random verification, functional coverage, code coverage, assertions, methodology & philosophy. Expert in System Verilog, Verilog, and OVM/UVM verification methodology. Have working experience on AMBA interface protocols Knowledge of Verilog/System Verilog, digital simulation, and debugging is a must. Experience with Perl, Python or similar scripting languages will be helpful.

As a RTL Packet Processing Engineer at Eridu AI India Private Limited, a subsidiary of Eridu Corporation based in Saratoga, California, USA, you will play a crucial role in defining and implementing industry-leading Networking IC. Your primary responsibility will be to design and architect solutions for high-speed networking devices with a focus on latency optimization, quality of service (QoS) support, CAMs, and routing tables. By implementing designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks, and conducting thorough testing and validation, you will contribute to the development of cutting-edge Networking devices. Your role will involve analyzing and optimizing pipelining architectures to enhance performance metrics, providing support for various networking protocols and standards related to input and output queues, including Ethernet, and troubleshooting and resolving complex issues related to packet queuing. Collaboration with cross-functional teams, including hardware engineers, firmware developers, and system architects, will be essential to investigate and address networking challenges effectively. To qualify for this position, you should hold a ME/BE degree with a minimum of 8-15 years of experience, possess working knowledge of system Verilog and Verilog, and demonstrate prior experience with ownership of memory subsystems. Your expertise in designing and optimizing packet pipelining and QoS mechanisms, familiarity with ASIC design methodologies, simulation, and verification tools, and experience with Ethernet/PCIe networking protocols will be crucial. Strong analytical and problem-solving abilities, attention to detail in troubleshooting and debugging, and effective communication skills will enable you to collaborate efficiently in a team environment and present technical information to diverse audiences. Joining Eridu AI will offer you the opportunity to contribute to the future of AI infrastructure, working alongside a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for this role will be determined based on your skills, experience, qualifications, work location, market trends, and compensation of employees in comparable roles.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. In this position, you will closely interact with the product definition and architecture team, develop implementation strategies to meet quality goals, define block-level design aspects, lead a team of engineers on RTL coding, drive design quality checks, and work towards delivering key design collaterals. Desired Skillset for this role includes a good understanding of low power microarchitecture techniques, AI/ML systems, computer system architecture, high-performance design techniques, NoC Design principles, Verilog/System Verilog, SOC DFT, and logic design principles. You will also work with stakeholders to discuss collateral quality, identify solutions, and collaborate with Power and Synthesis teams on use cases. Qualcomm is an equal opportunity employer committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact Qualcomm. It is expected that employees abide by all applicable policies and procedures, including security and confidentiality requirements. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is for individuals seeking a job at Qualcomm, and unsolicited submissions will not be considered. For more information about this role, please contact Qualcomm Careers.,

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,