NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B.Tech./ M.Tech or equivalent experience 5+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innova Additional Job Description Looking for an experience Verification Staff/Architect Engineer, who will be responsible Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers etc.) which goes into System-on-chip (SoC) for smartphones, tablets and other product categories. In this position you will be expected to plan and implement IP/Cluster/Formal verification flows for the Infra IPs. Also expected to coordinate with different Design and SOC teams throughout the IP development cycle. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Responsible for Quality sign off and required documentation Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM based verification Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL) Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Qualification : Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics 9 -12 years of experience Experience with UVM and ARM Bus protocols. tor, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74460 Job Description Summary: Digital design engineer developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. Candidate will take a supporting or leading role depending on experience relative to other team members, but regardless of experience level, candidate will be involved in all aspects of the design process from system conceptualization to mass production. For example, candidate will participate in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and full-chip mixed-signal verification. Responsibilities will also include detailed documentation, test vector development, lab test and evaluation, customer support, and other activities as required for the achievement of high volume production. Responsibilities: Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development Validation of silicon functionality, behavior, and performance Job Requirements Master's with 7-10 years of IC design experience or PhD with 4-6 years of IC design experience Strong motivation to contribute to all facets of chip design from conceptualization to release to production Working knowledge of digital IC circuit design in an HDL synthesis environment Working knowledge of digital verification and testing techniques Good verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a team Working knowledge of UNIX operating systems Additional skills (one or more of these are highly desirable): Experience with digital design at geometries ranging from 130-40 nm Experience with digital IO interfaces such at I2C, SPI, etc. Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience leading a team of digital designers, either formally or informally Experience with embedded processor design and firmware/software development, especially for 8051 or ARM cores Competence in exploring digital and firmware system/architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSP Experience with memory generators and MBIST Low power design and implementation techniques Familiarity with DSP techniques and algorithms Experience with Phase-locked-loops, Frequency Synthesizers or CDR circuits. Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3+ years’ experience in unit and subsystem level verification. Worked on coverage driven constraint random verification. Strong in System Verilog, UVM, Test planning Sound experience in testbench (stimulus, agent, monitor, checker) development. Worked in the verification having c-based reference model inside the testbench Exposure in scripting (Perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

MTS Silicon Design Engineer Bangalore, India Engineering 65529 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Silicon Design Verification Engineer The role: An RTL Design Verification Engineer role in our Security IP (SECIP) development team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our verification engineers will work on block level functional verification and its closure, and/or on subsystem level integration and verification for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications. The person: A talented hardware/firmware co-design/verification engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystem design and verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop and maintain block level IP and MP subsystem verification architecture, testbenches, test methodology and infrastructure Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology, C-DPI directed test methodology, formal proof verification methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests Triage regressions, debug simulations, analyze coverage, work/resolve technical issues with design, verification and other teams to achieve verification closure Participate in MP subsystem specification, influence IP micro-architecture development (design for verification aspect), design and execute reusable test methodology across individual MP subsystems Debug and solve integration issues with SoC Integration and SoC DV teams Provide technical leadership in verification methodology development and critical problem resolution if as advanced level team members Provide project execution leadership in term of technical assignment ownership, technical mentorship, task planning through divide and conquer, task progress reporting and forecasting if as advanced level team members Preferred experience: BSc with a minimum of equivalent 5 years relevant experience; or MSc with a minimum of equivalent 3 years; or PhD in a directly related research area and a minimum of 1 year A minimum of equivalent 10 years relevant experience if as advanced level team members Proven understanding of MP subsystem and/or common hardware datapath accelerator architectures as well as deep knowledge of applicable state-of-art verification methodology and best practices, if as advanced level team members Proficient in System Verilog, object oriented programming, and scripting (using Ruby, Perl, Python and Makefile) Proven skills in creating UVC and other UVM components. Experience with C-DPI and Formal Verification techniques are valuable assets. Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA) Proven experience with ASIC verification tools: simulation, debugging, linting, power aware simulation, etc. Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates Academic credentials: Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Master's Degree preferred. #LI-PS1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Senior Silicon Design Library Verification Engineer Bangalore, Karnataka, India No longer accepting applications Date posted Nov 14, 2024 Job number 1784581 Work site Up to 50% work from home Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview The Microsoft Silicon Engineering and Solutions Team is seeking passionate, driven and intellectually curious engineers to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas like Global Design Libraries, RTL & VIP Design, Design Verification, Validation, Simulation/Debug, Coverage and SoC integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our Design/Verification engineers so that they can deliver cutting-edge silicon solutions for Microsoft. Qualifications Required: BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. 6+ years of experience in FrontEnd Digital Design and Verification. Well-rounded and familiar with most Front-End Tools, Flows and Methodologies. Strong Experience working with Verilog/SV/UVM based IP development. Experience with Logic Design Compilation, Simulation tools and flows Expertise in one of the following areas: Design compile, elaboration and filelist/libraries handling. IP packaging, release and qualification IP integration Additional Preferred: MS in Electrical Engineering, Computer Engineering, Computer Science or equivalent work experience. 8+ years of relevant experience. Strong background in owning and maintaining design/verification IPs End to end and handling releases. Good understanding with Standard cells, memories and behavioral modeling of design. Hands on expertise getting an IP through Frontend qualification (lint, cdc, rdc, synth, low power..) and successful release. Exposure to understand design functionality of existing IP, understand connectivity and apply incremental improvements. Good background and exposure to FE VLSI design cycle. Hands on experience working with IP Design simulation debug flows. #SCHIEINDIA #AHSI Responsibilities For all CAD roles, you will: Be part of a central FE CAD team that drives common FE methodologies for SoC and IP design. Be the expert in your domain and act in partnership with the execution team. Independently own, drive and maintain Global Design/Verification Library components and manage releases to multiple SoC projects. Provide leadership to the design community for the CAD domain for which you are responsible. Work with stakeholders across the Microsoft Silicon group to collect library design requirements. Develop, enhance, and integrate common design and verification IP for organization-wide use. Work with EDA vendors to adopt the most optimal solutions for silicon verification and design. Mentor junior team members and summer interns. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. No longer accepting applications

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced virtual interface solutions such as Accelerated Verification IP’s and Virtual Bridges solutions for Cadence’s hardware emulation and prototyping platforms. Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 8+ years industry experience We’re doing work that matters. Help us solve what others can’t.

### Job Description: ASIC Design Verification Engineer **Location:** - Bangalore, Chennai, Hyderabad, Noida,Malaysia, Germany. **Experience Range:** 5 to 20+ years **Key Responsibilities:** - Develop and execute test plans to verify complex ASIC designs. - Utilize System Verilog (SV) and UVM methodologies for verification tasks. - Perform functional, formal, GLS (Gate-Level Simulation), power, and CPU verification. - Conduct IP and subsystem-level verification, ensuring robust verification of high-speed protocols. - Work closely with RTL designers to understand design specifications and requirements. - Write and maintain C/C++ test benches for verification environments. - Perform coverage analysis and drive coverage closure. - Debug issues found during verification and work with design teams to resolve them. - Participate in design and verification reviews, providing insights and suggestions for improvements. - Develop verification models and ensure their accuracy and performance. **Qualifications:** **Design Verification Engineer & Junior Verification Engineer:** - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - Minimum 3 years of experience in ASIC design verification. - Proficiency in System Verilog, UVM, and C/C++. - Knowledge of functional, formal, GLS, power, and CPU verification methodologies. - Experience with high-speed protocols and IP verification. - Strong debugging and problem-solving skills. - Excellent communication and teamwork abilities. **Senior Verification Engineer:** - All the qualifications of a Design Verification Engineer. - Minimum 7 years of experience in ASIC design verification. - Demonstrated leadership in verification projects. - Strong experience in subsystem-level verification and high-speed protocols. - Proven track record in coverage closure and verification planning. **Lead Verification Engineer:** - All the qualifications of a Senior Verification Engineer. - Minimum 10 years of experience in ASIC design verification. - Extensive experience leading verification teams and projects. - Expertise in multiple verification methodologies and high-speed protocols. - Strong project management and leadership skills. **Senior Lead Verification Engineer:** - All the qualifications of a Lead Verification Engineer. - Minimum 12 years of experience in ASIC design verification. - Experience in managing large verification projects and multiple teams. - Expertise in formal, functional, GLS, power, and CPU verification. - In-depth knowledge of verification models and techniques. **Staff Engineer:** - All the qualifications of a Senior Lead Verification Engineer. - Minimum 15 years of experience in ASIC design verification. - Significant experience in driving and mentoring large verification teams. - Recognized as an industry expert in verification methodologies and high-speed protocols. - Strong strategic vision and ability to influence product development. **Preferred Skills:** - Experience with different models of a product. - Familiarity with advanced verification tools and environments. - Ability to handle multiple tasks and projects concurrently. - Strong interpersonal and communication skills. - Demonstrated ability to mentor and train junior engineers. **Benefits:** - Competitive salary and benefits package. - Opportunity to work on cutting-edge technology and projects. - Professional development and career advancement opportunities. - Collaborative and innovative work environment. **How to Apply:** Interested candidates should send their resume and cover letter to sushma.siddaroda@tessolve.com Please specify the position you are applying for in the subject line Show more Show less

Lead Verification Engineer Experience: 10+ Years Location:[Bangalore| Ahmedabad | Pune| Hyderabad] Employment Type: Full-Time Job Description: We are seeking a highly skilled and motivated Design Verification Engineer with 10+ years of hands-on experience in SoC verification. The ideal candidate will be responsible for developing and executing comprehensive verification plans for high-performance SoCs, collaborating with cross-functional teams, and ensuring quality standards are met throughout the verification cycle. Key Responsibilities: Drive SoC Design Verification efforts for complex projects, ensuring thorough validation of functionality and performance. Develop and implement verification strategies, including test plans and test benches for both low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed interfaces (PCIe, Ethernet, CXL, MIPI, DDR, HBM). Conduct Gate-level simulations and power-aware verification using Xprop and UPF. Collaborate with architects, designers, and pre/post-silicon teams to define and validate verification requirements. Implement and analyze System Verilog assertions and coverage (functional, toggle, code). Guide and mentor junior verification engineers while fostering a collaborative and innovative team environment. Ensure verification signoff criteria are met, with complete and accurate documentation. Contribute to continuous improvement of verification methodologies and best practices. Integrate third-party VIPs from Synopsys and Cadence. Required Skills & Experience: Strong expertise in UVM and System Verilog-based verification environments. Hands-on experience with: SoC-level and IP-level verification DDR, HBM, Xprop, and UPF-based simulations Processor-based SoC verification environments (native, Verilog, System Verilog, UVM) Proficiency in verification tools like VCS, Xsim, waveform analyzers. Solid experience in scripting (Shell, Makefile, Perl) and C-SystemVerilog handshaking. Strong understanding of test practices and adherence to verification quality standards. Problem-solving mindset with excellent analytical and debugging skills. Qualifications: Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field. 10+ years of relevant experience in SoC design verification. Show more Show less

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role In this role, you will focus on the verification of CPU and chip-die (Cdie) level Power Management features for our server-class microprocessors. Your work will ensure that our processors achieve optimal power efficiency without compromising performance. You will collaborate closely with architecture, design, and post-silicon teams to validate and debug power management features, contributing to our cutting-edge AI compute solutions. As part of our team, you will be at the forefront of innovation, helping us deliver high-performance, energy-efficient products. The Design Verification team at Ampere is dedicated to ensuring that every product meets the highest standards of quality and efficiency. We are a collaborative, fast-paced group, committed to leaving no stone unturned in our verification processes. What You’ll Achieve Define requirements for power management verification at both sub-system and full-chip levels. Develop detailed test plans focused on power management features for both pre-silicon and post-silicon environments. Architect, design, and implement test benches and verification environments specifically for power management. Create targeted and random test generators to identify power-related bugs. Analyze and debug power management failures, driving rapid resolution. Develop coverage monitors and achieve targeted coverage metrics for power management features. Define and execute post-silicon validation plans for power management, supporting accelerated product launches. About You B.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience, or M.Tech with 2+ years of experience. Strong experience in hardware verification, particularly in power management for IPs or SoCs. Proficient in industry-standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools. Experience in developing verification environments using languages such as SVTB UVM/OVM. Proficiency in programming languages like C, C++, Perl, and Python for automation tasks. Experience in automating design, verification, and validation tasks related to power management. Familiarity with ARM, RISCV, or x86 assembly language programming is beneficial. Understanding of CPU architecture, power management techniques, coherent fabrics, and interconnects is a plus. Excellent written and verbal communication skills, with a strong attention to detail and analytical/problem-solving abilities. What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law. Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.  Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. “Unsolvable” is a foreign term, and you don’t do “unfair.” Your focus on the customers’ needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDA’s Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic · You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDA’s Questa products and services. · You’ll fosters a climate conducive to help grow customer satisfaction with Siemens’ tools by helping them successfully deploy new flows and methodologies. · Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. · You’ll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. · You’ll provide key expert advice and contribute to technical campaigns in other regions. · Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. · Work with Account Managers and the world-wide teams for forming strategies and driving Siemens’ tools for customer projects to enable business success for Siemens EDA. · Become a trusted advisor to your customers. · Will have moderate travel within India and abroad We are not looking for superheroes, just super minds · You’re a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. · You’ve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. · Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification ( Clock Domain Crossing - CDC & Reset Domain Crossing - RDC ) on designs · Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected · Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus · Low power verification techniques using UPF and CPF is a plus · Exposure to static timing analysis (STA) flows involving SDC is a plus We’ve got quite a lot to offer. How about you? This role is based in Noida and you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. Siemens EDA is a world leader in EDA Tools business and has been present in India since 1997. We, at Siemens EDA, enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled engineer with 6-10 years of experience, passionate about developing cutting-edge emulation solutions for industry-standard protocols such as PCIe, CXL, and UCIe. You possess a strong background in software development using C/C++ and synthesizable RTL development with Verilog. Your deep understanding of digital design concepts, HDL languages, and scripting languages like Python or Perl will be invaluable in this role. You thrive in collaborative environments, have excellent communication skills, and are adept at solving complex problems. Your ability to interact with customers during deployment and debug processes will ensure successful implementation and satisfaction. A B.E/B.Tech/M.Tech in Electronic & Communication or Computer Science Engineering is essential. Knowledge of ARM architecture, UVM, and functional verification, along with experience in emulation, will be a significant advantage. What You’ll Be Doing: Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth implementation. Collaborating with cross-functional teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys' emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys' position as a leader in chip design and verification solutions. What You’ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriented programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus. Who You Are: A collaborative team player with excellent communication skills. A problem-solver with a keen eye for detail and a passion for innovation. Adaptable and able to work effectively in a fast-paced, dynamic environment. Customer-focused, with the ability to handle deployment and debugging challenges efficiently. Committed to continuous learning and staying updated with industry advancements. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on developing and enhancing emulation solutions for cutting-edge semiconductor technologies. Our team collaborates closely with various departments to ensure the highest quality and performance of our products, driving innovation and excellence in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

🚀 About the Role We're hiring an experienced FPGA Firmware Engineer to develop and integrate high-speed digital systems for cutting-edge defence and aerospace applications. You'll work on complex RTL logic, high-speed interface protocols like 10G Ethernet and JESD204B/C, and mentor junior engineers in a mission-critical development environment. If you’re passionate about FPGA design and want to contribute to indigenous strategic technologies, we’d love to meet you. 📍 Location : Chennai | 🕒 Full-Time | 🧭 Experience : 3–5 Years No. of Vacancy : 01 🎯 What You’ll Do Design and implement RTL code (VHDL/Verilog) for FPGA-based systems (Xilinx/Intel). Integrate and validate 10G Ethernet, JESD204, and AXI-based IP cores. Collaborate with hardware teams for board bring-up and system-level debugging Optimise firmware for high-speed data processing, signal acquisition, and control loops. Simulate, verify, and debug designs using tools like Vivado, ModelSim, and Logic Analysers. Mentor a team of junior engineers and ensure adherence to coding standards. Contribute to documentation and compliance (DO-254, AS9100). Interface with cross-functional teams, including QA, hardware, and system engineering. ✅ What We’re Looking For B.E./ B.Tech or M.E./ M.Tech in ECE, EE, or related fields. 3–8 years of FPGA development experience in defence/aerospace or high-reliability domains. Hands-on experience with Vivado/Quartus, ModelSim/QuestaSim, and constraint-based timing closure. Strong understanding of 10G Ethernet, JESD204B/C, CDC, and high-speed digital design. Proficiency in scripting (Tcl, Python) and hardware debugging tools. Experience working with embedded soft cores (MicroBlaze, Zynq, or Nios II) is a plus. Team leadership or mentoring experience preferred. 🌐 Nice to Have Worked on radar, EW, or signal processing systems. Familiarity with MIL-STD, ARINC 818, or custom defence protocols. Prior engagement with DRDO, BEL, HAL, or Indian defence projects. 🛡 Why Join Us Work on indigenous, mission-critical defence systems. Be part of a growing high-tech R&D environment. Get opportunities to lead, innovate, and mentor. Secure and process-driven workplace with a focus on national development. Tips: Provide a summary of the role, what success in the position looks like, and how this role fits into the organisation overall. 📩 Apply Now If you're ready to take the lead on high-performance FPGA systems and mentor the next generation of engineers, apply now or send your profile to admin@indrainsignia.co.in Show more Show less

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. www.silabs.com Meet the team: The Baseband Modem Design group, in HYD, is primarily responsible for designing and developing cutting-edge WIFI modem solutions which are integrated into low-power/line-powered SoCs used in Wireless-IOT products. The group is responsible for the RTL implementation of the new WIFI standards required in the IOT space market. The team actively collaborates with signal processing experts in defining the algorithms and implementing them. The team also verifies core modem functionality and works with extended Verification team to verify all the System level usecases involving the baseband modem. It also handles the pre-Si and post-Si validation. Responsibilities: Develop complex communications or signal processing blocks for wireless-IOT products. Understanding of OFDM/signal processing is strongly desired Collaborate with System Engineers to drive the definition of wireless blocks to meet product requirements. Proficiency in Matlab/C is strongly preferred Micro-architecture and RTL design of modules using Verilog/System Verilog HDL coding, adhering to quality standards. Prepare and hold Architecture, Design, and Verification reviews with technical staff throughout project lifecycle Pre-silicon verification utilizing a combination of block/chip-level test benches. Validation/bring-up of designs on silicon, providing support to cross-functional teams Apply Low-power digital circuit design concepts Skills required: Demonstrated ability to work with Systems team to micro-architect and design complex digital subsystems Understand Matlab algorithm implementation and translate to effective RTL micro-architectures Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers (like vc, Questasim), and power analysis tools Experience with logic synthesis, timing constraints and timing closure Experience in working with backend team to optimize design for power performance and area Experience with scripting and automation. Knowledge of Python, Perl, and Tcl Experience with revision control and configuration management systems (such as Perforce, Git, Methodics) Excellent written and verbal communications skills Demonstrated ability to generate high output in a self-driven manner Experience Level: 4-6 years in Industry Education Requirements: Master’s /Bachelors degree in Communications/Electronics Engineering Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law. Show more Show less

This is not a job. This is a founding opportunity to architect the future of computing. THE VISION: JSA LAABS is developing NeuroCore - the world’s first production-ready Cognitive Processing Unit that will fundamentally transform how artificial intelligence processes information. We’re not incrementally improving existing architectures; we’re creating an entirely new category of computational hardware that thinks like the human brain while operating with unprecedented efficiency. Major tech giants, including NVIDIA and leading-edge computing companies, have already expressed strategic interest in our technology before our official launch. THE OPPORTUNITY: We are seeking ONE exceptional VLSI architect to join our founding team as we prepare to revolutionize neuromorphic computing. This is not a traditional employment opportunity - this is a chance to become a founding architect of the next computing revolution. THE FOUNDING TEAM MEMBER WE SEEK: Technical Excellence Required: • Deep VLSI Expertise: Master-level understanding of Verilog/SystemVerilog, RTL design, and PNR flows • Advanced System Integration: Proven experience with AXI/AMBA and other protocols, PCIe implementation, and NoC architectures • Architectural Vision: Ability to design complex, multi-domain systems from concept to silicon • Neuromorphic Understanding: Experience or strong interest in brain-inspired computing architectures (Preferred) • Compiler Development: Background in hardware-software co-design and optimization (Valued Plus) Leadership Qualities Essential: • Visionary Thinking: Sees beyond current limitations to revolutionary possibilities • Team Leadership: Natural ability to inspire, guide, and coordinate technical teams • Communication Excellence: Can articulate complex technical concepts to diverse stakeholders • Responsibility Ownership: Takes full accountability for deliverables and outcomes • Strategic Mindset: Understands business implications of technical decisions THE FOUNDING TEAM PROPOSITION: What We Offer: ✅ Founding Team Position: Core decision-making authority in company direction ✅ Profit Sharing Agreement: Direct participation in company success without equity dilution risk ✅ Salary Acceleration: Immediate competitive compensation once revenue begins (targeting Q2 2025) ✅ Technical Leadership: Lead architect role for groundbreaking neuromorphic hardware ✅ Industry Recognition: Your work will be published, patented, and industry-leading ✅ Strategic Partnerships: Direct collaboration with major tech companies already expressing interest What This Is NOT: ❌ Traditional salaried employment opportunity ❌ Risk-free corporate position ❌ Suitable for salary-driven professionals ❌ Entry-level or learning opportunity THE COMMITMENT: We are bootstrapped and focused entirely on building revolutionary technology. Every founding team member invests their expertise, time, and energy into creating something that will fundamentally change the computing landscape. Current Status: All founding team members, including leadership, are operating without immediate salary to focus 100% on product development and market positioning. Future Trajectory: With major industry players already expressing strategic interest and our technology demonstrating unprecedented capabilities, we are positioned for rapid revenue generation and market disruption. WHY NOW IS THE MOMENT: • Competitive Advantage: Our architecture solves fundamental efficiency problems that major players cannot address with traditional approaches • Industry Validation: Pre-launch interest from NVIDIA and other industry leaders validates our technological approach • Founding Opportunity: This is the last opportunity to join at the founding level before institutional partnerships and scaling IMPORTANT NOTICE: This opportunity is exclusively for founding-team caliber professionals who: • Understand that the greatest rewards come from building revolutionary technology • Are motivated by impact and innovation over immediate financial security • Possess the technical excellence and leadership capability to help build an industry-defining company • Recognize that profit sharing in a successful technology company far exceeds traditional salary employment. If you are primarily motivated by salary, traditional employment benefits, or risk-free opportunities, this position is not suitable for your career goals. Ready to architect the future of computing? Let’s build something extraordinary together. You can even send your work/resume to: vidhi.waghela@jsalaabs.com Show more Show less

Design Verification: Experience : 4 years Location : Hyderabad and Bagalore. Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience Must have good communication skills and the ability to work in a team environment. Preferably having experience in architecture such as x86 or ARM domain based SOCs having SOC/IP performance verification background is added plus Interested please share your updated resume to janagaradha.n@acldigital.com Show more Show less

Job Title: Senior Engineer - FPGA Location: Ahmedabad, Pune, Bangalore Experience level: 5+ Years In depth knowledge with VHDL/Verilog/System Verilog, RTL design, FPGA design, and FPGA design tools. Complete FPGA development flow from logic design, place & route, timing analysis closure, simulation, verification, and validation Experience with Xilinx/Intel FPGA families and corresponding development tools Vivado/Quartus Experience in verification/simulation tools Modelsim/Questa-sim etc. Troubleshooting and debugging FPGA implementations on hardware boards Experience with debugging HW/SW issues and the use of equipment/tools such as oscilloscope, logic analyzer, Chipscope/ILA/Signal Tap Ability to understand synthesis reports, perform timing analysis and write FPGA design constraints Hands-on experience on communication protocols (UART/I2C/SPI etc.) and bus interfaces (AMBA/AXI etc.) Good understanding of digital electronics and design practices Ability to work independently as well as in team Effective interpersonal, communication, presentation and reporting skill Qualifications: Minimum B.E./B.Tech in Electronics/E&TC/ECE About eInfochips · eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure. Along with Arrow’s $30B in revenues, 20,100 employees, and 349 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 200,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect. InfochipsInc. is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, genderidentity, national origin, veteran or disability status. eInfochips (Arrow) COVID-19 Vaccination Policy: eInfochips (Arrow) requires employees to provide proof of full COVID-19 vaccination by December 1, 2021, for all positions located in CO and for business units within immix Group and Zeus. All other employees will be required to identify vaccination status by December 1, 2021. Arrow COVID-19 Vaccination Policy: Arrow requires all new employees in the United States to provide proof of full COVID-19 vaccination prior to beginning work, except where prohibited by law. Show more Show less

Experience: 4 to 12 Years. Location: Bangalore. Must have hands-on experience coding in System Verilog/UVM. Experience developing testbenches for block level or IP level verification. Experience working on subsystem or SoC level would be helpful. Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules. Developing and maintaining block level test benches. Vplan, regression and coverage closure. Work on testbenches with real number modeling. Netlist and Gate level simulations. Notice Period: 30 to 90 days Show more Show less

SSOC Design Verification Engineer - Senior / Lead / Sr. Lead Experience: 5 to 12 Years Location: Hyderabad / Bangalore Job Requirement Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience Must have good communication skills and the ability to work in a team environment. Preferably having experience in architecture such as x86 or ARM domain based SOCs having SOC/IP performance verification background is added plus. About Company ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future. www.acldigital.com Show more Show less

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What You’ll Be Doing Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What We Need To See BS / MS or equivalent experience. 4+ years of design experience. Experience in RTL design of complex design units for at least two or three projects. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways To Stand Out From The Crowd Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Leadership experience in leading small 2-3 member teams. Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1965573 Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation. Qualifications BE/BTech/ME/MS/MTech Job Responsibilities Experience: 10+ Years Candidate must be able to generate RTL/handle scalable designs up to 48 billion Gates. Should be able to modify/update the designs to stress Flip-Flops/Wires/Gates/Input Outputs. Should be able use various available scalable compile/Runtime flows for large scalable designs. Should be able to profile and identify the slow performance areas and work with R&D on enhancements. Should be proficient in Verilog/ System-Verilog, scripting and exposure to Emulation platform is a must. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain, extend, and enhance existing DFT IP like LBIST We’re doing work that matters. Help us solve what others can’t. Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. #disw We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. At Siemens, we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow’s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Siemens Software. Where today meets tomorrow Show more Show less