Senior FPGA & DSP Engineer (Satellite / SDR)

Job Title: Senior FPGA & DSP Engineer (Satellite / SDR)

Role Summary:

We are seeking an experienced FPGA Engineer to lead the development of our Software-Defined Radio (SDR) modem. You will translate complex signal processing algorithms (Modulation, FEC, Filtering) into high-performance FPGA logic and integrate them with our Edge AI architecture.

Key Job Responsibilities:

• Modem Core Design: Design and implement high-speed DSP blocks for satellite communications (DVB-S2/S2X standards, QPSK/8PSK Modulators, Viterbi/LDPC Decoders).
• SDR Interface: Develop logic to interface with RF Transceivers (AD9361/AD9371) and high-speed converters via JESD204B/C.
• System-on-Chip (SoC) Integration: Work with Xilinx Zynq/MPSoC platforms to partition designs between Programmable Logic (PL) and Processing System (PS/ARM).
• AI Hardware Acceleration: Collaborate with the AI team to implement hardware accelerators for real-time Rain Fade prediction (ACM) and signal classification.
• Lab Validation: Bring up and debug custom hardware using Spectrum Analyzers, Vector Signal Generators, and ChipScope/SignalTap.
• Optimization: Optimize RTL for timing closure, resource utilization, and power consumption (critical for our solar/remote terminals).

Technical Skills:

• HDL: SystemVerilog, Verilog, VHDL (SystemVerilog is preferred for modern verification).
• DSP: MATLAB & Simulink (for algorithm modeling before coding).
• SDR Tools: GNU Radio, Ettus UHD, or ADI IIO Scope.
• Interfaces: AXI4 (Stream/Lite), JESD204B, Ethernet (1G/10G), PCIe.

Tools:

• Xilinx Vivado
• Vitis (Priority)
• Intel Quartus.

Basic Qualifications:

• Bachelor's or Master's degree in Electrical Engineering with a focus on Digital Communications or Signal Processing.
• 5+ years of experience in FPGA RTL design and verification.
• Critical: Deep understanding of Digital Signal Processing (FFT, FIR/IIR Filters, DDC/DUC, NCOs).
• Experience implementing communication standards (DVB, LTE, Wi-Fi, or 5G).
• Proficiency in C/C++ for embedded Linux driver development.

Preferred

• Experience with Satellite waveforms (DVB-S2, DVB-RCS2).
• Experience with Adaptive Coding and Modulation (ACM) implementation.
• Knowledge of High-Level Synthesis (HLS) to convert C/C++ algorithms to FPGA logic.
• Familiarity with AI/ML deployment on FPGAs (Xilinx Vitis AI or TensorFlow Lite Micro).
• Previous work with RF-SoC or Analog Devices Pluto/BladeRF platforms.