Fpga Verification Engineer

3 - 6 years

10 - 20 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

FPGA Verification Engineer with System Verilog and UVM experience to verify FPGA designs used in semiconductor plasma etchers.

Role & responsibilities

  • Must own and drive requirements, design, and implementation of verification solutions including System Verilog and UVM testbench infrastructure development.
  • Plan, develop, implement and execute testcases to uncover the design bugs.
  • Implement block and top level testbenches using SV/UVM.
  • Assist design, setup, and write software to control lab test setups for FPGA validation.

Preferred candidate profile

  • Bachelors or Masters in Electronics or related engineering fields;
  • Experience working on FPGA/ASIC verification for 3 to 6 years;
  • Good understanding and experience working with System Verilog and Universal Verification Methodology (UVM) based verification;
  • Experience in writing UVM testbench components: Drivers, Monitors, Sequencers, Agents, Scoreboards, etc.;
  • Experience in preparing the testplan from the requirements and implementing directed as well as constrained random testcases;
  • Experience working with Verification IPs: integrating the existing ones and creating new ones as per the requirements;
  • Experience with simulation tools such as Siemenss Questasim or others for FPGA/ASIC verification;
  • Experience running the regressions and analyzing/enhancing the coverage metrics;
  • Understanding of the designs implemented in Verilog and/or System Verilog;
  • Knowledge of the protocols such as SPI, I2C, EtherCAT, AXI, etc.;
  • Experience using version control systems such as GIT, SVN, etc.
  • Good communication skills and experience working with geographically distributed teams.

Preferred Qualifications:

  • Experience working with Xilinx Zynq SoC based design/verification;
  • Knowledge of embedded systems development/validation;
  • Experience modeling signal processing path and algorithms in MATLAB and port them to the verification environment, and, work with MATLAB models to create simulation stimulus.
  • Experience working with scripting languages such as Make, Shell, TCL, etc.;

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