Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary General Summary: Bachelors /Masters degree in Engineering Relevant experience of 2-12 yrs in any of the mentioned domain - Design/Verification/ Implementation Will be working on cutting-edge Wireless Technology (IEEE 802.11) team. Strong fundamentals in core areas: Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Design You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Strong communication skills to work with design teams worldwide Verification Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C As a design verification engineer you will work on developing IPs catering to upcoming Wifi standards like 802.11bn and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise. Implementation Candidate will be responsible for next generation WLAN hardmacro implementation Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO Extensive experience in UPF based power intent and synthesis Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3064190 Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Systems Engineering General Summary As a PCIe Architect Lead within the NoC Systems team, you will play a pivotal role in shaping the architecture of the next generation of PCIe (Peripheral Component Interconnect Express) Switches. This position requires a deep understanding of PCIe technology, strong architectural skills, and the ability to lead and collaborate with cross-functional teams. Key Responsibilities Architecture Development: Lead the design and development of the next-generation PCIe Switch architecture. Define and document the architectural specifications, ensuring they meet performance, reliability, and scalability requirements. Collaborate with hardware and software teams to ensure seamless integration of the PCIe Switch into the overall system. Technical Leadership Provide technical leadership and guidance to the NoC Systems team. Mentor and train junior engineers, fostering a culture of innovation and continuous improvement. Stay abreast of the latest industry trends and advancements in PCIe technology. Other Responsibilities SoC Interconnect for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. This position includes but no limited to:- NoC Systems lead and is part of BDC infrastructure (NoC/Interconnect) core team Responsible for system requirement collection, use-case understanding and preparing specification for interconnect working with adjacent IPs Actively work with QPA team, SoC team, verification team, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sites Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions Remains abreast with next generation ARM/Amba specification, PCIe specification, QNoC changes and Low Power Technology changes to guide and influence the NoC Design, Verification, Power and Physical Design teams in improving their KPIs, processes leading to better Qualcomm products at efficient NRE Advises and leads small groups of less experienced engineers in evaluating various design features to identify potential flaws, compatibility issues, and/or compliance issues; reviews design evaluations conducted by less experienced engineers Troubleshoots multiple advanced issues with NoCs; uses a variety of debugging tools and methods Exercises exceptional creativity to innovate new ideas and develop innovative NoC systems and IP solutions without established objectives or known parameters Minimum Qualifications: 7 to 12 years of experience in SoC design/Systems, NoC design/Systems Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts Good knowledge of Digital Design and RTL development Hands-on experience with SoC Design, Verilog RTL coding Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification and silicon debug Working knowledge of Lint, CDC, PLDRC, CLP etc Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Should possess effective communication and leadership skills Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering. PhD in Computer Science, Engineering, Information Systems, or related field and 15+ years of Hardware Engineering or related work experience is welcome Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3066994 Show more Show less

Role Description Role Proficiency: Independently execute mid sized customer projects in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor owning any one task of RTL Design/Module. Provide support and guidance to engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams On time quality delivery approved by the project manager and client Automate the design tasks flows and write scripts to generate reports Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and client Measures Of Outcomes Quality –verified using relevant metrics by UST Manager / Client Manager Timely delivery - verified using relevant metrics by UST Manager / Client Manager Reduction in cycle time cost using innovative approaches Number of papers published Number of patents filed Number of mandatory trainings attended adhering to training goals Outputs Expected Quality of the deliverables: Ensure zero bugs are present in the design / circuit design. Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of tasks and work performed Timely Delivery Ensure project timelines as laid out by the client or program manager are met Meet intermediate tasks delivery for other team members to progress Calling out for help and support in the case of delay in tasks delivery New Skills Development Participate in training – skilling someone and also getting skilled in newer technologies Take up new areas of project development learn on the job and deliver Team Work Participation in team work and supporting team members at the time of need Able to take up additional tasks in-case of any team member(s) not available Able to hand hold junior team members to explain the project tasks and support to deliver Work dedication to go beyond the call of duty to ensure deadlines and quality are met Innovation & Creativity Approach towards repeated work by automating tasks to save design cycle time Participation on technical discussion training forum white paper etc Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience in one or more tools) Technical Knowledge:a. IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills and ability to interact with team members and clients equally Strong analytical reasoning and problem-solving skills with attention to details Ability to understand the standard specs and functional documents Ability to deliver the tasks on-time in a quality fashion per quality guidelines and GANTT Well versed with the available EDA tools and able to use them efficiently Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project Knowledge Examples Knowledge of project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc. Understanding of the design flow and methodologies used in the designing Understand the assigned tasks and have sufficient knowledge to execute the project tasks assigned by the client / manager as per known skills Additional Comments The person should have hands on experience(>8 Yrs.) on full custom Memory design & architectures, Characterization, Layout design, net-listers, complete SRAM Design verification at compiler level (not only at instance level) covering both design and layouts. The person should ensure to populate and publish Execution plan, Design Quality plan, DFMEA, Publish project health along with reporting of any risk and mitigation strategy. “ Skills Memory design and compiler,SRAM design,Design quality plan Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ ASIC VERIFICATION ENGINEER The Role We are currently looking for MTS ASIC Verification Engineers who will be involved in all aspects of AMD's next generation Data center network products. This includes verifying designs using the latest UVM standard and developing comprehensive test plans to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages. Our products are aimed at making Data Centre Networking solutions more effective. This is a highly strategic and important part of AMD’s business, targeting a set of customers that includes the most successful internet and cloud companies in the world. Successful candidate will work alongside an experienced design and architecture teams and will thus have enormous opportunities for learning and self-development. The position is likely to require some travel. THE PERSON: Creative innovator and thinker who loves technical problems and detail-oriented tasks Exhibits relentless commitment to help the team meet quality and development goals on schedule with high quality Drives to learn and perform at their highest potential in a technical capacity Thrives in both a team environment and in individual contribution. Able to lead a small team of engineers working towards a common objective Able to learn independenly and acquire new skills required for the job Communicates openly and clearly in meetings, presentations, emails, and reports KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Experience with PCIe and/or Ethernet protocols Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration Good understanding and hands-on experience in the UVM concepts and System Verilog language Scripting language experience: Python, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to network processors. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. Show more Show less

At Vicharak , we're on the forefront of a computing revolution. Just like the pioneers at Bell Labs in 1947 who witnessed the birth of the transistor, we're shaping the future of semiconductors with our innovative FPGA technology. Unlike traditional processors, FPGAs allow us to programmatically change their inner circuitry, opening up new horizons in parallelism, speed, and computing. We've developed VAAMAN , a cutting-edge hardware system that combines FPGA and SBC, and we're on the lookout for talented individuals who share our passion for this field. We're seeking researchers, developers, designers, engineers, and architects to join us in building the next generation of computing. What You Will Learn: Software languages such as C/C++ , Python, and HDL languages Verilog and System Verilog. Master FPGA tools like Vivado, Radiant. Develop the ability to learn, adapt, tackle challenges, and perform effectively. Gain insights into the workings of everything from keyboards to complex servers. What You Will Work On: You will be contributing to our groundbreaking projects across our Acceleration framework, focusing on AI Acceleration, Software Acceleration, and the optimization of peripheral systems. Gain hands-on experience with Verilog and System Verilog, becoming proficient in the fundamental aspects of these languages. Simulation and Testing: Utilize advanced simulation tools to rigorously test designs, ensuring they meet stringent functional requirements. Cross-Functional Collaboration: Work closely with various engineering disciplines to integrate FPGA designs into broader system architectures and resolve any arising issues. FPGA Development and Validation: Develop FPGA requirements and code for logic design, create self-checking test benches, conduct unit tests, perform synthesis, timing analysis, and support Built-In-Test (BIT) processes. Validate these designs by loading them onto FPGA boards for real-world testing. High-Speed Serial Interfaces: Address challenges related to high-speed serial interferences within FPGA designs. Collaboration and Teamwork: Collaborate effectively with cross-functional teams, leveraging diverse expertise to enhance project outcomes. Continuous Learning: Stay at the forefront of industry practices and technological advancements to ensure our methods and designs are state-of-the-art. Preferred Skills: Good understanding of digital electronics and design practices. Strong VHDL/Verilog Programming skills. In depth knowledge of RTL design, FPGA design, and FPGA design tools. Complete FPGA development flow from logic design, place & route, timing analysis closure, simulation, verification, and validation. Strong troubleshooting and debugging FPGA implementations on hardware boards. Hands-on experience on communication protocols (UART/I2C/SPI). Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Excellent interpersonal, communication, collaboration and presentation skills. https://vicharak.in/ Show more Show less

Greetings from Synopsys!!! I hope this message finds you all well! At Synopsys Inc, we are looking for Senior Design Verification Engineer and expertise in System Verilog and UVM methodology skills for an exciting project. If you're open to exploring this opportunity, I would love to discuss it further. Please feel free to reply to this email or we can chat over the phone at your convenience. I believe this could be a great match for both of us. Experience: 5+yrs to 15years Location: Bengaluru & Noida Expertise in UVM/OVM/SOC and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for verification projects using VMM/OVM/UVM methodologies . Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Taufiq Hussain Talent Acquisition, Sr Staff | People | mobile: +91 9148401555 | email: taufiq@synopsys.com

Objectives of this role Design and develop hardware products, including circuit boards, components, and systems, while adhering to industry standards and best practices. Generate and maintain hardware design, testing, and quality control documentation. Participate in design reviews, risk assessments, and product validation activities to ensure compliance with regulations. Collaborate with cross-functional teams, including design, development and customer support, to provide feedback and input on product design, performance optimisation, and manufacturability. Your tasks Conduct thorough testing and validation of hardware products to ensure compliance with specifications, requirements and quality standards. Perform root cause analysis and troubleshooting of hardware defects and implement preventive measures for malfunctions to minimise future occurrences. Stay up to date with the latest advancements in hardware testing methodologies and apply them to improve the overall quality of our products. Required skills and qualifications Bachelors degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of demonstrable experience as a computer hardware engineer. Strong knowledge of hardware design principles, testing tools, equipment, and techniques (mainly PCB designing). Excellent analytical and problem-solving skills with an eye for detail and precision. Ability to work independently and manage multiple tasks simultaneously. Preferred skills and qualifications Proficiency in programming languages, like C/C++ and/or Verilog/VHDL. Familiar with industry regulations in India, like ISO 9001, ISO 13485, BIS and RoHS. Knowledge of hardware regulatory requirements, such as FCC and CE. Strong communication, teamwork, and project management skills.

Design Verification Engineer (5 to 12 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 5 t o 12 Years Openings: 8 Positions Preferred - Immediate to 45 Days (Notice Period) Job Location: ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Notice Period-Prefer less Notice period or serving. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills Communication and collaboration skills to work effectively with cross-functional teams Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: AMBA, AXI, PCIE, USB, MIPI

In fast changing markets, customers worldwide rely on Thales. Thales is a business where brilliant people from all over the world come together to share ideas and inspire each other. In aerospace, transportation, defence, security and space, our architects design innovative solutions that make our tomorrows possible. Senior Technical Lead - Design Optimization for FPGAs Essential Specifications: Masters / PhD in Electrical Engineering, Computer Science, or a related field with at least 10 years of experience on FPGA based designs, design optimizations and problem solving. Strong understanding of digital logic fundamentals and computer architecture. Proficiency in FPGA programming techniques. Experience with timing analysis and optimization for FPGA designs. Excellent skills in Verilog programming language. Experience using Vivado or Questa Sim EDA tools. Desirable Specifications: Knowledge of RISC-V architecture. Effective presentation skills to communicate complex ideas. Familiarity with verification techniques using UVM. Responsibilities: Work on a variety of design optimization problems for FPGA-based systems. Collaborate with the team to develop innovative solutions for performance improvement, power optimization, and area reduction. Implement designs using FPGA programming languages like Verilog. Conduct timing analysis and optimize designs to meet performance requirements. Utilize Vivado or Questa Sim EDA tools for design and validation. Stay informed about the latest advancements in FPGA design optimization. Document research findings and project progress accurately. Participate in team meetings, providing valuable insights and suggestions.

In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 8+ Years of Exp

Our vision is to transform how the world uses information to enrich life. Join an inclusive team focused on one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solution we create help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design. Unique Opportunities Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4, LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on cross functional tasks that can widen your skill set. About Team For nearly 40 years, Micron Technology, Inc. has redefined innovation with the world s most advanced memory and semiconductor technologies. we're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. Our Global team is growing and we are looking for a passionate Memory Circuit Design & Verification Engineer in Micron Technology s DRAM and Emerging Memory Group (DEG) in India. Responsibilities Participate in simulating, analyzing and debugging pre-silicon full chip designs by applying leading edge verification technique Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Core Requirements Analytical capability for complex gate level circuit designs Basic understanding of CMOS circuit designs Familiar with both SPICE and Verilog simulations Good communication skills and ability to work we'll in a team Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

As a member of the AECG Product Validation and Solutions Teams within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen 6, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. KEY RESPONSIBILITIES: Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans Pre-Silicon and Post Silicon validation for new PCIe enabled blocks Responsible for IP design, Silicon bring up, Validation and IP release Work in collaboration with the Global teams PREFERRED EXPERIENCE: Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog Proficient in RTL simulation tools (VCS, Modelsim) Knowledge of high-speed interfaces including, PCIe, CXL, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer Experience in developing system or IP prototypes using FPGAs Strong knowledge of IP/SOC design methodologies Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles Knowledge of C/C++ is an added advantage ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B. Tech. / M. Tech or equivalent experience 5+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e. g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate #LI-Hybrid

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . www.silabs.com Meet the team: The Baseband Modem Design group, in HYD, is primarily responsible for designing and developing cutting-edge WIFI modem solutions which are integrated into low-power/line-powered SoCs used in Wireless-IOT products. The group is responsible for the RTL implementation of the new WIFI standards required in the IOT space market. The team actively collaborates with signal processing experts in defining the algorithms and implementing them. The team also verifies core modem functionality and works with extended Verification team to verify all the System level usecases involving the baseband modem. It also handles the pre-Si and post-Si validation. Responsibilities: Develop complex communications or signal processing blocks for wireless-IOT products. Understanding of OFDM/signal processing is strongly desired Collaborate with System Engineers to drive the definition of wireless blocks to meet product requirements. Proficiency in Matlab/C is strongly preferred Micro-architecture and RTL design of modules using Verilog/System Verilog HDL coding, adhering to quality standards. Prepare and hold Architecture, Design, and Verification reviews with technical staff throughout project lifecycle Pre-silicon verification utilizing a combination of block/chip-level test benches. Validation/bring-up of designs on silicon, providing support to cross-functional teams Apply Low-power digital circuit design concepts Skills required: Demonstrated ability to work with Systems team to micro-architect and design complex digital subsystems Understand Matlab algorithm implementation and translate to effective RTL micro-architectures Verilog RTL design with demonstrated experience of taking designs through the silicon development lifecycle to production Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers (like vc, Questasim), and power analysis tools Experience with logic synthesis, timing constraints and timing closure Experience in working with backend team to optimize design for power performance and area Experience with scripting and automation. Knowledge of Python, Perl, and Tcl Experience with revision control and configuration management systems (such as Perforce, Git, Methodics) Excellent written and verbal communications skills Demonstrated ability to generate high output in a self-driven manner Experience Level: 4-6 years in Industry Education Requirements: Master s /Bachelors degree in Communications/Electronics Engineering Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support #LI-DK1 #LI-Hybrid Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 8 – 12 years experience in Design Verification Expert Knowledge in IP Verification Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface Must have expert knowledge in coverage driven test planning Must have expert knowledge in architecting configurable environments Must have very strong System Verilog and UVM background Must be able to lead the team technically in all aspects, must be able to drive multiple projects Past experience leading and managing teams highly desired Excellent Communication and Presentation Skills Ability and desire to learn new methodologies, languages, protocols etc. is required Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SENIOR VERIFICATION ENGINEER – SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience in SV/ UVM based verification project. Good debug skills is a must. Experience in building components like Scoreboard, functional coverage & writing sequences using SV/UVM based Verification environment One of the following experiences is important: Experience in Video/Display domain in particular DP, oLDI, MIPI CSI/ DSI Experience in any one high speed protocol like USB3, PCIe, MIPI, Unipro etc Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia Singapore SwedenStockholm USADelaware Location - Bengaluru,Chennai,Hyderabad,Noida

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

TECHNICAL LEAD – DFT SmartSoC is looking for a smart and enterprising leader with expert knowledge in DFT to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking. You will be responsible for leading and managing a team, client communication, and project execution. Job Responsibilities- Lead an internal DFT team, executing projects for an offshore client Manage the team and their technical and leadership growth Manage all interactions with the client Desired Skills and Experience- 7+ years of experience in DFT, mainly Scan Architecture, ATPG & MBIST Experience in planning scan chains, running scan insertion flow Experience in latest Cadence tool set Genus & Modus Experience in ATPG for Stuck@, TFT, IDDQ & Path delay faults with tough coverage targets Experience in MBIST architecture, generation and implementation Experience in AECQ100 requirement standard is a big plus Experience in working with a multi-site team is a big plus Experience in working on critical time-bound projects is a big plus Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible„¢ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Key Responsibilities: Understand and Enhance Existing FPGA Architecture: Analyze and comprehend current FPGA designs and architectures. Identify areas for improvement and optimization within existing systems. Implement enhancements to improve performance, efficiency, and functionality. Develop Modular Architectural Approaches with a Focus on Testability: Design modular FPGA architectures to facilitate ease of testing and integration. Ensure that new designs are scalable and maintainable. Incorporate best practices for testability into the design process. Collaborate with Software, Hardware, and System Teams: Work closely with cross-functional teams to ensure FPGA designs meet system requirements. Communicate effectively with software developers, hardware engineers, and system architects. Participate in design reviews and provide feedback to other team members. Develop RTL Code, Perform Logic Synthesis, Timing Analysis, and Timing Closure: Write and optimize RTL (Register Transfer Level) code for FPGA designs. Conduct logic synthesis to translate RTL code into gate-level designs. Perform timing analysis to ensure designs meet timing constraints and achieve timing closure. Create Test Benches and Simulation Tools for Verification: Develop comprehensive test benches to verify the functionality and performance of FPGA designs. Utilize simulation tools to test and validate designs before implementation. Debug and resolve issues identified during the verification process. Troubleshoot and Improve Building Block Modules: Identify and resolve problems in FPGA modules to enhance performance and reliability . Continuously improve the design and functionality of FPGA building blocks. Document troubleshooting processes and solutions for future reference. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Proficiency in hardware description languages such as VHDL or Verilog. Experience with FPGA design tools and platforms (e.g., Xilinx Vivado, Altera Quartus). Strong understanding of digital design principles and practices. Excellent problem-solving skills and attention to detail. Ability to work collaboratively in a team environment and communicate effectively with diverse teams. Preferred Skills: Experience with high-speed digital design and signal processing. Familiarity with scripting languages (e.g., Python, Tcl) for automation tasks. Knowledge of system-level integration and testing methodologies. Experience in low-power design techniques and optimizations. The role of an FPGA engineer is dynamic and requires a strong technical foundation, creativity in design, and the ability to work well within a multidisciplinary team to develop cutting-edge digital systems. Top of Form Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug