2369 Verilog Jobs - Page 18

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum of 7 years of experience in the field Proficiency in DVT pattern experience Experience with ATE and functional vectors generation Understanding of Stimgen flow Prior experience with AMD is preferred Skills: Strong debugging skills Experience with MBIST, JTAG, and Phy-loopback NoteCandidates are encouraged to provide a detailed resume showcasing their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Redefine how verification is done!Were hiring Functional Verification Engineers for Bangalore to tackle IP/SoC verification, cache coherency, and more.Experience Required4"“18 YearsKey Skills: High-speed protocols, low-power simulations (UPF), System Verilog/UVMBe a part of the innovation journey! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Title: ASIC RTL Design Engineer Position Experience Level: 6 to 10 years Location: Bangalore : We are seeking a highly skilled and experienced ASIC RTL Design Engineer to join our team in Bangalore. The successful candidate will have 6 to 10 years of relevant experience and will play a crucial role in the design and integration of RTL components for complex ASIC projects. The candidate should possess a strong background in RTL UPF, SoC Design Integration, and multi-domain UPF methodologies. Additionally, a strong understanding of resolving VSI issues is required to excel in this role. Key Responsibilities: RTL UPF Experience: The ideal candidate should have a proven track record of working with RTL UPF (Unified Power Format) to efficiently manage power intent for ASIC designs. SoC Design Integration: Experience in the integration of RTL components into System-on-Chip (SoC) designs, ensuring seamless functionality and performance. Multi-Domain UPF: Proficiency in working with multi-domain UPF to address power management across different aspects of the design. VSI Issue Resolution: Ability to identify and rectify VSI (Voltage Storm Immunity) issues to enhance the reliability and robustness of the ASIC design. Additional : In addition to the core responsibilities, candidates who have experience in addressing UPF constraints and issues during the synthesis process and Engineering Change Orders (ECOs), including mitigating RTL-UPF mismatches, will be considered favorably. This position offers an exciting opportunity to work on cutting-edge ASIC projects, pushing the boundaries of design and innovation. If you are a seasoned RTL Design Engineer with the requisite experience and skills, we encourage you to apply and join our dynamic team in Bangalore. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Take the lead in advanced design verification!Were looking for a Senior Design Verification Engineer in Bangalore to work onHBM, DDR, UCIe, PCIe protocols, and more.Key Skills: System Verilog/UVM, protocol verificationExperience Required3+ YearsJoin our team and help shape groundbreaking designs. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Strong communication skills, both written and verbal Experience: At least 8 years of professional experience in the field Skills: Proficiency in Trace, Cross-Trigger, JTAG, and AXI protocols Expertise in security protocols, real boot processes, Debug mode, Warm reset, power management, and LP-UPF Previous experience with AMD is considered an advantage NoteInterested candidates should submit a detailed resume highlighting their relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Number of Open Positions4 Experience: 4+ years Location Hyderabad : We are looking for a highly skilled and experienced Gate-Level Simulation Engineer to join our team. The ideal candidate should have a minimum of 4 years of experience and possess a strong background in gate-level simulation (GLS). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is essential for this role. Key Responsibilities: Collaborate with cross-functional teams to define and execute gate-level simulation test plans. Develop and implement gate-level simulation strategies for complex digital designs. Conduct gate-level simulations to verify the functionality and performance of digital designs. Work closely with design and verification teams to identify and resolve issues at the gate level. Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. Ensure compliance with industry standards and best practices in gate-level simulation. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in gate-level simulation. Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Prior experience in gate-level simulation is essential. Familiarity with gate-level simulation tools and methodologies. Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work in a dynamic and fast-paced environment. If you are a motivated and experienced Gate-Level Simulation Engineer with a strong background in SV, UVM, and a passion for ensuring the quality and reliability of digital designs at the gate level, we encourage you to apply for this position. Join our team and contribute to the success of our cutting-edge projects. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad

Number of Open Positions: 7 Experience: 4 to 7+ years Location: Bangalore : We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. Key Responsibilities: DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities. Verification: Verify DFT features and ensure their correctness through simulation and formal verification. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field. 4 to 7+ years of experience in DFT-DV engineering. Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG. Proficiency in industry-standard EDA tools for DFT implementation. Experience with low-power design and PHY-LP integration is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: Minimum 8 years of experience in functional Design Verification (DV) Proficiency in low-power UPF-based verification Strong debugging skills Skills: In-depth understanding of power gating and power management techniques Familiarity with AXI and SMN protocols Previous experience with AMD is advantageous Location: Hiring for Bangalore (BLR) or Hyderabad (HYD) locations NotePlease provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Let your ideas power the next wave of technology!Were hiring Design Verification Engineers for Bangalore and Hyderabad.Experience Required4"“18 YearsKey Skills: HSIO protocols like PCIe, DDR5, HBM, USB, low-power simulationsWork on cutting-edge verification projects and take your career to new heights. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

Qualifications: Bachelor’s or Master’s degree in Electrical Engineering or related field (BE/BTech/M.E/M.Tech) Excellent communication skills, both verbal and written Experience: 5-8 years of experience in RTL Design with exposure to synthesis OR 8+ years of experience in RTL Design Strong understanding of digital basics Proficiency in RTL coding (Verilog), IP design, and RTL integration Hands-on experience with LINT, CDC, and RDC Experience in writing UPFs and CLP/VCLP checks Familiarity with synthesis flow and validating design constraints Specific domain knowledge in ARM protocols, PCIe, Ethernet, RISC V, DDR, etc. Strong scripting knowledge Responsibilities: Understand the overall ASIC flow and effectively collaborate with multiple teams such as DV, DFT, Synthesis/Implementation, and PD teams Ability to take on the role of a Technical Manager while maintaining hands-on contributions NoteInterested candidates should provide a detailed resume highlighting relevant experience and skills. Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaHyderabad

Ready to make vehicles smarter and saferJoin us as an Automotive Functional Safety Verification Engineer in Hyderabad!Key Skills: FuSa verification, ISO 26262 standards, System Verilog/UVMExperience Required4+ YearsWork on cutting-edge safety innovations in automotive systems. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaHyderabad

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop and maintain Linux device drivers, bare-metal software, and embedded Linux applications. Configure and integrate Linux device trees for embedded platforms. Develop models for QEMU or other virtual platforms to simulate hardware components. Design and automate tests using Python and Pytest for software validation. Contribute to and collaborate with open-source projects and communities. Debug and optimize software on embedded and virtual platforms. Collaborate with cross-functional teams for hardware-software integration. Apply system architecture knowledge (ARM, Microblaze, RISC-V) in development and debugging. Skills Must have 2-4y exp Expert knowledge and hands-on experience in C, C++, make, python, Pytest, git Experience with Linux Device trees and Linux or baremetal driver development Experience with Embedded Linux and Embedded System development Experience with writing models for QEMU or other virtual platforms Experience with collaboration with Open Source projects Strong knowledge in ARM/Microblaze/RISCV system architecture is considered a plus SystemC, RTL, Verilog and AMBA knowledge is considered a plus Nice to have Effective communication and problem-solving skills Other Languages English: B2 Upper Intermediate Seniority Regular

Dear Connections, Position Vacant : "Design Verification" [DV] Location : Bangalore Work Mode : WFO No of days working : 5days Experience : 5-10 years Availability : Immediate to 30 days joiners Company Description: Welcome to Semi Leaf consulting Service! Semi Leaf consulting firm is a team of experts that help to find candidates with specialized skills in industries such as Semiconductor/VLSI/EDA & Embedded domains. Role Description: This is a full-time opportunity for "Design Verification" with SEMI LEAF located in Bengaluru. The candidate will be responsible for day-to-day tasks associated with present role with our clients. Job Description : 1. DV engineers with Subsystem and IP Development Prefer exposure to AXI, Coherence background, PCIe, DDR 2. Engineer experienced in SV, UVM and C. 3. Must-have experience in SOC. 4. Has understanding on AXI, AHB protocol. 5. Working knowledge of SoC level verification of IPs like IPU, Graphics will help. 6. AMD flow experience is preferred. 7. Processor based verification, RISC-V 8. Hands-on experience in System Verilog, OVM/UVM based constrained random verification. 9. Experience with scripting languages like Python, Perl, skill, TCL or equivalent to automate flows is a plus. 10. Hands on Testbench bring up, integrating third party VIPs, digital design, verification, debugging, and waveform debug 11. Worked on USB2/USB3/PCIE/UFS/MIPI/DDR PHY's functionality & Loopback tests concepts 12. Experience on SoC level Interface/Configurability of HSIO PHY Registers 13. Knowledge on HSIO PHY Controller and PHY + controller test case porting knowledge If you are an engineer with suitable experience looking for a new opportunity, Share your updated resume to vagdevi@semi-leaf.com References are highly appreciated!

We are now looking to hire strong performance verification engineers with a sharp understanding of CPU and memory architecture. NVIDIA makes some of the fastest CPUs in the world and is solving problems, with its vast arsenal of CPUs, GPUs and SW, in areas such as High-performance computing, Automated driving, Medical imaging and much more! We are seeking highly motivated engineers to join this dynamic and innovative team that owns performance alignment of CPUs and CPU fabrics made by NVIDIA! Do you want to be part of the team that explores and defines the next generation of CPUs? What will you be doing: Responsibilities will include development of test plans and strategies, develop simulation environments, system bring-up, validation, and automation to deliver best-in-class CPUs. Develop and maintain CPU simulator infrastructure, hardware CPU test and performance infrastructure. Analyze and validate CPU and fabric performance, helping to understand current, and guide the development of future CPU products. Definition and development of tool chain and workflows that enables the full system performance alignment. Silicon based competitive analysis of NVIDIA CPUs. What we need to see: Master's or Bachelor's degree in EE/CS or equivalent experience 5+ years of experience preferably in the areas of CPU / SOC Performance Verification and Analysis Strong understanding of computer system architecture and operating system fundamentals. Hands-on experience with HDLs such as Verilog / System Verilog. Knowledge of verification methodologies and tools for IP and SoC level verification. Experience with System Verilog, C/C++, Python languages and relevant frameworks. Background with debug on Silicon. Ways to stand out from the crowd: Detailed knowledge of the ARM and/or x-86 architecture. Prior experience with performance analysis of CPUs. Experience with analysis and characterization of CPU workloads. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid

Agnisys is looking for freshers to join our team to work on high tech products for the Semiconductor industry. Agnisys is a leader in automating SoC development. It’s products are considered to be the most comprehensive and best in class. We offer a progressive, innovations-driven, learning environment. Don’t get pigeon-holed into one specific area when you can learn the intricacies of Design, Verification, Firmware and overall chip design all at one company! Not only that, you will be exposed to Product Validation, Customer Support and an Agile development environment. Agnisys focuses on research and development by participating in Accellera Systems Initiative, presenting in worldwide conferences, encouraging creative thinking and initiative. So if you value innovation and creativity and want to create a strong foundation for your career, join Agnisys today. Basic Requirements: Candidates should be B.Tech.CS & MCA freshers/graduate Basic Knowledge in Verilog, VHDL, SystemVerilog & C FPGA, EDA Tools, Linux, Perl, Python, Tcl, Bash scripting Should have excellent communication skills Ability to work independently with little supervision as well as ability to work within a team Excellent multi-tasking skills Self-motivated with strong team spirit Job Type: Full-time Pay: ₹22,000.00 - ₹22,001.00 per month Benefits: Health insurance Internet reimbursement Schedule: Day shift Work Location: In person

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years’ experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement Design Verification Engineer (Senior Level - 10+ years’ experience) Company: HCL Tech Job Summary: We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies. Responsibilities: Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification) Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team Champion best practices for verification code quality and participate in code reviews Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies Provide technical leadership and contribute to the overall verification roadmap for the team Qualifications: Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred) Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs Proven track record of successfully leading and executing verification projects In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages) Excellent leadership, communication, collaboration, and problem-solving skills Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines Benefits: Competitive salary and benefits package commensurate with experience and expertise Opportunity to lead and influence the verification of cutting-edge technologies Dynamic and challenging work environment with opportunities for professional growth and leadership development Recognition and rewards for outstanding contributions

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc. The role requires to work with architect and micro-architect team to understand define design specifications The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. Accountabilities Serve as a key contributor to FPGA design efforts. Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality through assertions, checkers, and scripting. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 5+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus. Familiarity with FPGA designs, use-cases, and design considerations is a plus. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

System Design & Architecture : Lead architectural planning and design of software systems prioritizing scalability, reliability, and maintainability. Development & Coding : Write clean, efficient, and well-documented code. Implement robust testing, including unit and integration tests. Project Leadership : Drive projects from concept to delivery. Break down tasks, estimate effort, track milestones, and manage technical risk in collaboration with PMs and stakeholders.

Location: Hybrid Job Type: Full-Time Posted Date: 6/30/2025 About The Role Job Overview: We are looking for an experienced Senior Design Verification Engineer with a strong background in System Verilog and UVM , capable of independently owning and driving the verification of blocks, subsystems, or full SoCs. The ideal candidate will have expertise in industry-standard protocols and power-aware verification, with hands-on experience in building and executing scalable verification environments. Must-Have Skills: Strong hands-on experience with System Verilog (SV) and UVM. Proficient in Testbench Architecture & Development Expertise in verifying at least one of the following protocols: o PCI Express, UCIe, CXL, or NVM o AXI, ACE, or CHI o Ethernet, RoCE, or RDMA o DDR, LPDDR, or HBM Key Responsibilities: Own and lead the verification of digital blocks, subsystems, or SoCs Develop scalable and reusable UVM-based verification environments Execute test plans, write test cases, and drive coverage closure Collaborate with architecture, design, and firmware teams Debug and root-cause issues across the design-verification stack Contribute to regression automation and continuous integration workflows Required Experience: 8+ years of hands-on experience in System Verilog/UVM-based design verification Strong understanding of IP, subsystem, and SoC level verification Experience in one or more of the following: o PCIe, UCIe, CXL, NVM o AXI/ACE/CHI bus protocols o Networking interfaces (Ethernet, RoCE, RDMA) o Memory interfaces (DDR, LPDDR, HBM) o ARM or RISC-V CPU-based subsystems using C/Assembly Experience with Power-Aware Simulations using UPF If you are interested in this role, please mail your resume to hemanth@neualto.com or spoorthy@neualto.com

Role Overview: We are seeking a forward-thinking and tech-savvy FPGA Engineer to support the development and implementation of digital technologies across our operations. Key Skills Required: Design, simulate, and implement digital logic circuits on FPGAs using VHDL or Verilog Collaborate with hardware and software teams to integrate FPGA designs into larger systems Develop testbenches and perform functional simulations to verify FPGA designs Perform synthesis, place and route, and timing analysis using industry-standard FPGA toolchains (e.g., Xilinx Vivado, Intel Quartus) Debug and validate FPGA designs on target hardware using oscilloscopes, logic analyzers, and in-system debugging tools Optimize FPGA designs for performance, power, and resource utilization Document design specifications, development processes, and test procedures Stay updated with the latest FPGA technologies and best practices Educational Background: Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field Preferred Experience: 3+ years of hands-on experience in FPGA development and digital design Proficiency in VHDL or Verilog and familiarity with scripting languages like Tcl or Python Experience with FPGA development tools (Xilinx, Intel/Altera, Lattice, etc.) Preferably should have exposure to the latest RFSoCs Strong understanding of digital electronics, timing analysis, and embedded systems To apply, please send your resume to hr@sisirradar.com . Please include " FPGA Engineer " in the subject line.

Company Description Spandsons Horizon Engineering revolutionises the AEC industry by integrating sustainability, Design & Build of Infrastructures, Structural Engineering, AI, IoT, and innovative technologies into project management, Virtual Design Construction, and training programs. We are at the forefront of blending advanced technological solutions with environmental consciousness to drive progress and innovation. Our mission is to deliver cutting-edge engineering solutions while fostering a culture of continuous learning and development. Role Description This is a contract role for a VLSI Mentor / Guest Faculty specialising in Advanced Digital Systems & Low Power Design. This is an on-site role located in Salem. You will be instrumental in guiding 5th, 6th, and 7th-semester B.E./B.Tech students in advanced VLSI concepts and practical applications. This role offers a unique opportunity to directly impact the academic and career growth of 60 aspiring engineers. Key Responsibilities: Deliver engaging and in-depth sessions on: Advanced Digital System Design with Verilog HDL: Covering topics from Verilog HDL basics, combinational and sequential circuits, FSM design, to simulation and testing. Low Power VLSI Design: Including the need for low power design, power estimation and optimisation, dynamic power reduction techniques, clock/power gating, and leakage reduction techniques. Potentially other VLSI domains such as Digital Design Verification with SystemVerilog & UVM, Introduction to FPGA-Based Digital System Design, ASIC Design and Verification, and Introduction to RISC-V Architecture and FPGA Design, based on program needs. Provide hands-on guidance for lab assignments and projects, utilising tools like Xilinx Vivado, EDA Playground, ModelSim/Vivado, LTspice, Synopsys Design Compiler, ICC2, PrimeTime, VCS, Verdi, and FPGA boards. Facilitate interactive learning and encourage problem-solving among students. Ensure alignment of content with the recommended semester curriculum and prerequisites. Qualifications: Minimum of 4-5 years of verifiable industry experience in VLSI design, with strong expertise in Advanced Digital System Design and Low Power VLSI Design. Proficiency in relevant EDA tools and hardware platforms as listed above. Excellent communication and presentation skills. A passion for teaching, mentoring, and contributing to student development. Program Details: Total Students: Approximately 60. Schedule: Thursdays & Fridays (12 hours per week). Program Start Date: July 24th & 25th. Duration: Program for Semesters 5, 6, and 7. Benefits: Accommodation and food will be provided by the institution. Opportunity to make a significant impact on the next generation of VLSI engineers. Collaborate with a forward-thinking academic institution.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.

Silicon Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848529 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission Qualifications Required Qualifications: Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. Experience in Logic Design or Verification. Expereince with ASIC verification flow. Experience with Verilog, System Verilog, and UVM based testbench environment. Preferred Qualifications Knowledge of one of Ethernet, TCP/IP, PCIe, or High Speed Memory Technologies Good understanding of Computer Architecture Responsibilities Functional validation of ASIC SOC at Block, Cluster or Fullchip using UVM/C test bench Develop Test Plan and write unit tests for functional validation Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Logic Design Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848527 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an SOC RTL to PD Engineer to join the team. Qualifications Required Qualifications: MS with 2+ years of experience or BS with 4+ years of experience. At least 3+ years of experience applying digital design principles in SOC and/or IP development. Strong Static Timing Analysis background; understanding timing signoff fundamentals. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion. Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. Understanding in design closure challenges in power and clock domain crossings. Understanding reset and FIFO related design requirements. Preferred Qualifications Experience with FEV and industry standard tools such as Formality and/or Conformal Applied understanding of low power design principles. Highly Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Strong understanding in clock crossing techniques Strong understanding in IJPF (Low power intent). Ability to write scripts using Perl, TCI, Python etc. Familiarity with Industry standard interface protocols is a plus. Good verbal and written communication skills. Responsibilities Ensure high quality deliverables from RTL to Physical Design Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results Create, analyze, and maintain timing constraints/SDCs Analyze and drive UPF solutions for low power checks Drive RTL to Synthesis FEV clean Collaborate with RTL and Physical Design team to address design feedback and drive quality Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.