2371 Verilog Jobs - Page 19

Silicon Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848529 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission Qualifications Required Qualifications: Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience. Experience in Logic Design or Verification. Expereince with ASIC verification flow. Experience with Verilog, System Verilog, and UVM based testbench environment. Preferred Qualifications Knowledge of one of Ethernet, TCP/IP, PCIe, or High Speed Memory Technologies Good understanding of Computer Architecture Responsibilities Functional validation of ASIC SOC at Block, Cluster or Fullchip using UVM/C test bench Develop Test Plan and write unit tests for functional validation Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Logic Design Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848527 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an SOC RTL to PD Engineer to join the team. Qualifications Required Qualifications: MS with 2+ years of experience or BS with 4+ years of experience. At least 3+ years of experience applying digital design principles in SOC and/or IP development. Strong Static Timing Analysis background; understanding timing signoff fundamentals. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion. Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. Understanding in design closure challenges in power and clock domain crossings. Understanding reset and FIFO related design requirements. Preferred Qualifications Experience with FEV and industry standard tools such as Formality and/or Conformal Applied understanding of low power design principles. Highly Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Strong understanding in clock crossing techniques Strong understanding in IJPF (Low power intent). Ability to write scripts using Perl, TCI, Python etc. Familiarity with Industry standard interface protocols is a plus. Good verbal and written communication skills. Responsibilities Ensure high quality deliverables from RTL to Physical Design Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results Create, analyze, and maintain timing constraints/SDCs Analyze and drive UPF solutions for low power checks Drive RTL to Synthesis FEV clean Collaborate with RTL and Physical Design team to address design feedback and drive quality Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Role: Functional verification Engineer Skills: UVM,Verilog or SystemVerilog, SOC, ASIC, AMBA Bus Protocols Location: Hyderabad Experience: 4-10 yrs Open Positions: 8 Client: AMD Notice Period- Immediate - 45 Days Skills: asic,amba,amba bus protocols,uvm,soc,systemverilog,verilog,functional verification,dv

Siemens EDA, a part of Siemens Digital Industries Software, is a global technology leader in electronic design automation. Our technologies enable companies around the world to develop new, highly innovative electronic products faster and more cost-effectively. Our customers use our solutions to push the boundaries of technology to deliver better products in the increasingly complex world of chip, board, and system design. Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. “Unsolvable” is a foreign term, and you don’t do “unfair.” Your focus on the customers’ needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDA’s Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDA’s Questa products and services. You’ll fosters a climate conducive to help grow customer satisfaction with Siemens’ tools by helping them successfully deploy new flows and methodologies. Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. You’ll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. You’ll provide key expert advice and contribute to technical campaigns in other regions. Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. Work with Account Managers and the world-wide teams for forming strategies and driving Siemens’ tools for customer projects to enable business success for Siemens EDA. Become a trusted advisor to your customers. Will have moderate travel within India and abroad We are not looking for superheroes, just super minds You’re a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. You’ve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification (Clock Domain Crossing - CDC & Reset Domain Crossing - RDC) on designs Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus We’ve got quite a lot to offer. How about you? This role is based in Noida and you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role Our MCU DV Engineer will work with multi-functional global teams to implement and verify next generation highly complex microprocessor-based SoC designs. Develop system-level and unit-level test plan for functional verification and performance verification, write test benches and coverage using System Verilog and UVM, write random and directed tests for correctness and performance of microprocessors. DV work at Ampere is interesting, challenging, and will expand your professional breadth and depth. We like to bring out the best in people, teach each other, and produce products that have value in the market. What You’ll Achieve You will be responsible for verifying the DDR5 memory controller and physical interface designs with the highest quality by partnering with the architecture and design teams. You will be responsible for developing complex test plans and driving the implementation and execution of the same across block level and SoC level test bench implementations. You will drive the closure of the verification cycle across x-prop, power-aware and gate level simulations About You B.Tech with 5 years or M.Tech with 3 years in Electronics / Computer Science Engineering or equivalent degree Understanding of the industry standard DDR4/DDR5 protocols Good verification experience, adept at UVM verification methodologies Development experience in languages common to the industry (e.g. Verilog, System Verilog, C, C++, Perl, Python). Exposure to different verification techniques such as x-prop, power-aware simulations Understanding of the gate level simulations Strong fundamentals of Cache coherence protocols, computer architecture Exposure to AMBA/AXI protocols and coherent fabric interconnect will be desired. Ability to work well in a team setting and contribute to the overall understanding of the team. What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Job Overview Work with Qualcomm's security architecture / IP and access control team on next generation SOC for smartphone, tablet, automotive and IOT product categories. is responsible for assisting product development teams throughout the company to apply secure HW design principles to individual blocks, computing cores, and at the SoC level. SW/HW co-design, HW development experience. Familiarity with debug architectures such as JTAG and ARM coresight are a plus Successful candidates will be able to engage with product teams independently with minimal supervision to detect and mitigate security vulnerabilities in hardware architecture and implementations, involve in access control issues at both SW and HW. Minimum Qualifications 6 to 12 years of industry or academic experience in Security are required. Additionally, applicants must have expertise in two or more of the following areas: Computer architecture and hardware based or assisted access control and security Mobile platform security, Secure Boot, Secure Storage, Access Control, Secure Debug, DDR protection ARM TrustZone, Virtualization Operating system security and hypervisor security languages: C/C++, Python, RTL Teamwork across various teams and geolocations. Able to communicate in English, both verbal and written. Preferred Qualifications The following skills/experience will be considered a plus: ARM architecture SoC security design Applied Cryptography Trusted Computing Working Knowledge on hardware firewalls for access control Knowledge on AI/ML is added advantage SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design is a plus Side channel attacks, power analysis and timing attacks on crypto elements is a plus Memory technology (DDR4, DDR5), storage technologies is (eMMC, UFS) is a plus Educational Requirements: Required: Bachelor degree and above, Computer Engineering and/or Electrical Engineering Experience Requirements: Bachelor’s/ Masters with 5-7+ years Systems Engineering or related work experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3065402

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Qualcomm modem team is looking for world-class RTL design engineers looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry leading devices. You will be contributing to RTL design and integration of one or more flagship Modem core IPs. Responsibilities include: Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Working collaboratively with block designers, verification, architecture, implementation, and post-silicon teams to resolve issues and ensure timely project execution. Collaborating with cross-functional teams, debugging and identifying issues, providing workarounds, and making recommendations on bug fixes. Skillset Required The candidate must have at least 1 to 4 years of front-end ASIC RTL design experience. The candidate must be strong in design micro-architecture and RTL coding (SystemVerilog / Verilog / VHDL). Other requirements include: Hands-on experience with multi-clock designs. Exposure to synthesis and STA. Awareness of low power and high-speed design. Knowledge of industry-standard front-end tool flows (lint, CDC, etc.). Strong critical thinking, problem-solving, and debugging skills. Good communication and interpersonal skills. Flexible to work with multi-geo teams. Minimum Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 9-13 years of hardware engineering or related work experience. OR Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 8-12 years of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 5+ years of hardware engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073973

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Setting up flows/process for quality checks, release management for different front-end flows. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

ASIC Design Verification Engineer, Staff The candidate will be part of the R&D in Solutions Group, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP verification using the latest verification methodology flows. Job Description The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. He/ She will work closely with RTL designers and be part of a global team of expert Verification Engineers. Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding and analysis, meeting quality metric goals and regression management. Requirements: Must have BSEE in EE with 4 to 8+ years of relevant experience or MSEE with 3 to 7+ years of relevant experience in the following areas: Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to verification methodologies such as VMM/OVM/UVM/ is required. Exposure to Formal verification methodologies is highly desirable. Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired. Exposure to IP design and verification processes including VIP development is an added advantage. There will be strong focus on functional coverage-driven methodology. So, the corresponding mindset is a must. It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem-solving skills and show high levels of initiative. This position requires prior industry experience and is not open for college fresh grads. Location: Bengaluru

As an engineer of NVIDIA's Software Quality Assurance (QA) team, you will play a crucial role in orchestrating the Software Quality processes for CAD tools and flows that support all semiconductor products. You will be working on infrastructure and software used to test complex semiconductor devices, including developing in-house tools for Design for Test (DFT) using languages like C++, Python, and TCL. This role requires a diverse skill set and a willingness to tackle challenges head-on. Your responsibilities will include providing support for testing and validation processes, architecting automated and customizable Software Quality processes, crafting test plans and cases, automation of testing, maintaining regression testing frameworks, performing code reviews and testing, and ensuring the delivery of high-quality, bug-free software applications. You will collaborate closely with team members to provide DFT and DFP methodologies for cutting-edge chip designs and support the development of tools using C++, Python, and TCL. To be successful in this role, you should have a BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with a minimum of 4 years of experience in a Software QA role. You should possess knowledge of various software testing techniques, code reviews, testing tools such as TestRail or Zephyr, CI/CD tools like Jenkins and GitLab, and have skills in Python, TCL, or C++. Experience with defect tracking tools like JIRA and lab software and hardware support is also essential. To stand out, additional knowledge or experience with DFT, BDD processes, Verilog, ASIC design principles, and logic cells will be advantageous. NVIDIA is known for being one of the most desirable employers in the technology industry, attracting forward-thinking and talented individuals. If you are a creative and autonomous professional looking to make an impact, we encourage you to apply and join our diverse team today.,

As an Electronics Engineer in Ahmedabad on a full-time basis, you will be responsible for designing and optimizing low-noise analog front-end (AFE) circuits and efficient DC-DC power supply circuits. Your tasks will involve selecting and integrating high-resolution ADCs, precision op-amps, and mixed-signal conditioning circuits. Additionally, you will develop bias voltage circuits for detectors and work towards minimizing thermal drift. PCB layout for low-noise analog systems, including shielding, grounding, and EMI/EMC mitigation, will be part of your responsibilities. Collaboration with the FPGA team for sensor calibration and data acquisition is also expected. To excel in this role, you should have at least 5 years of experience in analog/mixed-signal design, preferably for sensors and imaging. Any previous work experience with ISRO would be a plus. Hands-on experience with low-noise pre-amplifiers, high-resolution ADCs, PCB design tools, DC-DC converters, LDOs, power sequencing, thermal electric cooler (TEC) drivers, thermal simulation tools, and low pass filters is essential. Familiarity with thermal IR detectors and knowledge of thermal stability techniques are desirable qualifications. Your educational background should include a B.Tech/M.Tech in Electronics Engineering or a related field. As an Embedded Systems Engineer (FPGA & Digital Design) in Ahmedabad on a full-time basis, you will be responsible for FPGA-based image processing, implementing real-time algorithms for imager on FPGA using VHDL/Verilog. You will optimize high-speed sensor interfaces for detectors and implement data compression/streaming using protocols like GigE, USB3, or custom protocols. Additionally, you will integrate microcontrollers (ARM Cortex, RISC-V) for system control, design digital logic circuits for peripheral interfacing, and collaborate on embedded firmware for real-time operation. System integration tasks will include bridging FPGA + MCU communication and debugging mixed-signal PCB designs. To succeed in this role, you should have at least 3 years of experience in FPGA + Embedded Systems, with a preference for imaging/sensor applications. Proficiency in VHDL/Verilog and experience with high-speed serial protocols is required. Hands-on experience with ARM Cortex, RISC-V, or PIC MCUs, along with familiarity with digital interfaces such as I2C, SPI, UART, and PWM, will be beneficial. Your educational background should include a B.Tech/M.Tech in ECE/Embedded Systems/Digital Electronics.,

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ yrs of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm / 28nm ETC) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, where you will be working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Your responsibilities will include deriving circuit block level specifications from top-level specifications, performing optimized transistor-level design of analog and custom digital blocks, running SPICE simulations to meet detailed specifications, and guiding layout design for best performance, matching, and power delivery. Key Responsibilities: - Derive circuit block level specifications from top-level specifications - Perform optimized transistor-level design of analog and custom digital blocks - Run SPICE simulations to meet detailed specifications - Guide layout design for best performance, matching, and power delivery - Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) - Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits - Conduct design reviews at various phases/maturity of the design Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and are interested in these exciting opportunities, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. Join ARF Design for a chance to work on advanced nodes with fast-track interview and onboarding processes.,

We are hiring PCIe engineers: -In-depth knowledge and experience with PCIe protocols upto Gen5 -Good experience of system Verilog -handson experience of working on UVM -Good to have scripting language Perl/Shell/python

Software Engineering Apprenticeship Noida, Uttar Pradesh, India Interns/Temp Intern Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration. Engineer your future with us! Play Video Job Description Category Interns/Temp Hire Type Intern Job ID 9299 Remote Eligible No Date Posted 17/07/2025 We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide and having fun in the process! Youll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today s innovations and spark tomorrow s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive both at work and beyond. What You ll Be Doing: Troubleshooting software programs in Emulation. Managing R&D SW regressions. Creating validation suites for feature enhancements. Learning and exploring new technologies. Networking with internal and external personnel on assigned tasks. What You ll Need: Should be a fresh graduate engineer in Computer Science or Electronics (2025/2024). Knowledge of coding (C/C++) and scripting (Perl, Python). Understanding of Data Structures and Basic Operating Systems Concepts. Knowledge of Verilog/VHDL and EDA tools is a plus. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: In-office Full-Time/Part-Time: Full-time Start Date: August/September 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply As an applicant your resume, skills, and experience are being reviewed for consideration. Phone Screen Once your resume has been selected a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. Interview You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via Zoom. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Roles and Responsibility Skill Job Description Open position Count .LIB timing file generation Experience Level - 2-3 years 1 Need resource with the following skills: .LIB timing file generation Verilog Modelling Analog design characterization - familiarity with Cadens spectre and Synopys Hspice Additional help with Analog Quality Checks : o EM/IR simulation Please find the below mentioned JD for the replacement hiring. 1. Embedded product knowledge like UFS and eMMC 2. Embedded c , c++ & python knowledge is must 3. Automation background is also major priority 4. Experience on debugging using T32 or any tools Experience : Within 5 Years.

What Youll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

Senior Staff Applications Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12246 Remote Eligible No Date Posted 17/07/2025 Alternate Job Titles: Senior Staff Applications Engineer Post-Sales Application Engineer Interface IP Technical Solutions Engineer IP Integration Staff Engineer Customer Success (IP) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a deeply skilled engineering professional with a passion for enabling the success of others. You thrive in a dynamic, customer-facing environment, where your technical expertise and problem-solving abilities are tested daily. You have a strong foundation in ASIC/SoC front-end design, with hands-on experience in RTL coding, synthesis, timing analysis, and formal verification. You re adept at debugging complex designs whether in simulation, emulation, or actual silicon and you understand the intricacies of at least one industry-standard protocol such as USB. Collaboration is at the heart of your work style: you communicate effectively with both customers and internal teams, translating technical needs into actionable solutions. You take initiative, anticipate challenges, and enjoy the satisfaction of resolving tough issues. Your high degree of self-motivation, personal responsibility, and analytical rigor ensures that you deliver results even under pressure. You are eager to share best practices, drive continuous improvement, and contribute to the broader success of your team and customers alike. If you are excited about tackling new challenges, committed to excellence, and ready to make a real impact in the semiconductor industry, you will find your place at Synopsys. What You ll Be Doing: Providing expert technical support to customers integrating Synopsys Interface IPs into their SoC designs. Analyzing and resolving complex issues related to IP configuration, integration, and usage across various platforms. Interfacing directly with customers to understand their design and verification flows, identifying both current and future needs. Collaborating with cross-functional teams to address and resolve customer challenges efficiently. Debugging and troubleshooting designs in simulation, emulation, and silicon environments. Driving the adoption of best practices and lessons learned from customer interactions back into product development. Proactively engaging with customers during integration and silicon debug phases to ensure successful deployment. The Impact You Will Have: Accelerating customer time-to-market by providing timely and accurate technical guidance. Enhancing customer satisfaction and trust in Synopsys IP solutions through effective support and problem resolution. Contributing real-world feedback to product development, improving the robustness and usability of Synopsys IP. Reducing post-sales escalations and ensuring smooth IP integration for major industry players. Fostering long-term customer partnerships by consistently exceeding expectations. Helping shape the direction of next-generation IP products based on customer needs and industry trends. What You ll Need: Bachelor s or Master s Degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. Minimum 8 years of relevant experience in ASIC/SoC front-end design, including RTL coding (Verilog), logic and clock tree synthesis, static timing analysis, and equivalence checking. Full understanding of digital design methodologies and tools, including formal verification. Domain knowledge of at least one interface protocol (e.g., USB); experience with additional protocols (PCIe, DDR, SATA, HDMI, MIPI, Ethernet) is a plus. Experience supporting at least one ASIC/SoC tape-out from concept to full production. Strong silicon debug and troubleshooting skills are highly desirable. Who You Are: Technically creative, results-oriented, and able to manage multiple priorities efficiently. Strong communicator who can explain complex technical concepts to diverse audiences. High degree of self-motivation and personal responsibility. Excellent analytical, reasoning, and problem-solving skills with keen attention to detail. Collaborative team member who thrives in cross-functional environments. The Team You ll Be A Part Of: You will join the Solutions Group at Synopsys, a highly collaborative team dedicated to delivering world-class IP solutions and customer success. Working closely with experts in design, verification, applications engineering, and product development, you will be at the forefront of supporting and enabling the most innovative semiconductor companies across the globe. Our team values knowledge sharing, continuous learning, and a proactive approach to solving the industry s toughest challenges. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Ciscos core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Ciscos ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelors or a Master s Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns. Why Cisco? #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we re "old" (36 years strong) and only about hardware, but we re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don t care. Tattoos? Show off your ink. Like polka dots? That s cool. Pop culture geek? Many of us are. Passion fo Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. 8+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs and leading projects from concept to verification closure. Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage. We’re doing work that matters. Help us solve what others can’t.

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74460 Summary Job Description Digital design engineer developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. Candidate will take a supporting or leading role depending on experience relative to other team members, but regardless of experience level, candidate will be involved in all aspects of the design process from system conceptualization to mass production. For example, candidate will participate in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and full-chip mixed-signal verification. Responsibilities will also include detailed documentation, test vector development, lab test and evaluation, customer support, and other activities as required for the achievement of high volume production. Responsibilities Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development Validation of silicon functionality, behavior, and performance Job Requirements Master's with 7-10 years of IC design experience or PhD with 4-6 years of IC design experience Strong motivation to contribute to all facets of chip design from conceptualization to release to production Working knowledge of digital IC circuit design in an HDL synthesis environment Working knowledge of digital verification and testing techniques Good verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a team Working knowledge of UNIX operating systems Additional skills (one or more of these are highly desirable): Experience with digital design at geometries ranging from 130-40 nm Experience with digital IO interfaces such at I2C, SPI, etc. Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience leading a team of digital designers, either formally or informally Experience with embedded processor design and firmware/software development, especially for 8051 or ARM cores Competence in exploring digital and firmware system/architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSP Experience with memory generators and MBIST Low power design and implementation techniques Familiarity with DSP techniques and algorithms Experience with Phase-locked-loops, Frequency Synthesizers or CDR circuits. Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting Who You Are Skilled in building robust verification environments with System Verilog, UVM, and C++, and confident driving verification plans independently. Bring a system-level mindset with experience integrating and verifying multi-IP clusters or SoCs. Strong in stimulus planning, debug, and coverage closure for subsystems like caches, NoCs, and memory hierarchies. Comfortable working on cross-IP features such as coherence and security at the cluster or SoC level. What We Need Bachelor’s or Master’s in Electrical Engineering, Computer Science, or a related field. Hands-on experience with System Verilog and UVM-based verification. Track record of driving subsystem or SoC-level DV projects, including integration and feature validation. Familiarity with AXI/CHI protocols, system IPs (debug, power mgmt), and multi-IP verification flows. What You Will Learn How to scale DV infrastructure for high-performance RISC-V clusters and SoCs. Verification strategies for multi-agent systems across CPUs, IPs, and interconnects. Best practices for integration-level planning and cross-IP feature convergence. Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: ASIC Verification THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: 4+yrs of proficient experience in SoC and IP level RTL verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Knowldgeable on AMBA protocols like APB/AHB/AXI etc Required protocols knowledge like USB, I3C, UFS, QSPI etc Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to ARM & RISCV architecture. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Scripting and programming experience using Perl/Python, TCL, and Make Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Job Description: We are seeking an experienced Team Lead with expertise in FPGA (Xilinx) and Embedded Linux to drive the development of a thermal imaging system comprising a thermal core, FPGA-based Accelerator, and an embedded Linux Multicore SOM. The system Shall process thermal images and display them on an OLED screen. Leading a team of development engineers, define architecture, ensure seamless integration between FPGA and Linux subsystems and deliver a high-performance, low-latency thermal imaging HW and SW solution. Key Responsibilities: Leading team of FPGA, Embedded Linux, and firmware engineers in designing and developing the thermal imaging software for the defined Architecture Architect and implement real-time thermal image processing pipelines on Xilinx FPGA (Zynq/Artix/Kintex) and multicore ARM based SOM Develop and optimize embedded Linux drivers and middleware for thermal data acquisition, processing, and display. Interface thermal sensors (e.g. LYNRED/ FLIR Lepton/IADIY series UC Bolometer cores,) with FPGA and Embedded Linux subsystems. Implement low-latency DMA, image processing algorithms (NUC, AGC), Noise cancellation Algorithm and display drivers Ensure seamless FPGA-Linux communication (AXI, UART, SPI, I2C,USB, custom IP cores). Define and enforce coding standards, version control (Git) and CI/CD pipelines. Optimize system performance for power, latency, and throughput. Collaborate with hardware engineers on PCB design, signal integrity, and thermal management. Conduct design reviews, assist in debugging, and validation with HW and SW tools. Review Design Documentation Required Skills & Experience: Min 10 years in FPGA (Xilinx Vitis/Vivado) + Embedded Linux development. Strong expertise in real-time image processing (thermal preferred). Hands-on experience with: Xilinx SoCs (Zynq, MPSoC), AXI, VHDL/Verilog, HLS (C/C++) Embedded Linux (Yocto, Buildroot), Device Drivers, U-Boot, Kernel Modules Sensor interfacing (I2C, SPI, MIPI), DMA, and low-level optimizations OLED,HDMI display controllers Proficiency in Python/C/C++ for embedded applications. Experience with thermal imaging cores. Knowledge of bare board bring-up, SW and HW debugging Prior work in defense, medical, or industrial thermal imaging is desirable . Experience with AI/ML acceleration on FPGA (TensorFlow Lite, PyTorch).will be added advantage

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated ASIC Digital Design Engineer with a passion for pushing the boundaries of technology. With a strong background in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI, you excel in functional verification flows and methodologies, particularly VMM, OVM/UVM, and System Verilog. Your expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation sets you apart. You possess fundamental knowledge of Analog and Digital mixed signal design, and your scripting skills in TCL/Perl/Python are top-notch. You are a team player with excellent communication skills, problem-solving abilities, and interpersonal skills, eager to deliver high-quality RTL and Simulation models to customers and support them through silicon bring-up and debug processes. What You’ll Be Doing: Develop and review the verification test-plan for multi-protocol 112G PHY IP (Serdes). Create and optimize the verification environment based on UVM. Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code). Deliver high-quality RTL and Simulation models to customers. Coordinate between RTL, Analog design, and Tech pub teams. Support customers with the integration and bring-up of IP in their simulation environments. Develop and deliver SV verification components for customer integration. Assist customers with silicon bring-up and debug issues when customer silicon is available. The Impact You Will Have: Ensure the delivery of robust and high-quality verification solutions for Synopsys’ high-performance PHY IPs. Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies. Enhance customer satisfaction through exceptional support and high-quality deliverables. Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches. Contribute to the development of industry-leading verification methodologies and best practices. Help maintain Synopsys’ reputation as a leader in chip design and verification solutions. What You’ll Need: B.Tech/M.Tech with 7+ years of relevant experience. Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI. Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog. Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation. Fundamental knowledge of Analog and Digital mixed signal design. Proficiency in scripting and automation using TCL/Perl/Python. Excellent debug and diagnostic skills. Who You Are: You are an innovative and detail-oriented professional with a strong technical background and a collaborative mindset. Your excellent communication skills, problem-solving abilities, and interpersonal skills make you a valuable team player. You thrive in a dynamic environment, continually seeking to improve processes and deliver high-quality results. Your passion for technology and dedication to customer success drive you to excel in your role. The Team You’ll Be A Part Of: You will join a dynamic and collaborative team focused on the verification of high-performance multi-protocol PHY IPs. Our team is dedicated to delivering innovative solutions and exceptional support to our customers, ensuring the successful integration and deployment of Synopsys IPs. Together, we drive technological advancements and set industry standards in chip design and verification. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.