As a Memory Layout Lead at Best-in-Class Semiconductor Memory IPs, you will be responsible for driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main focus will be on owning the complete layout strategy, from bitcell integration to periphery circuits, ensuring best-in-class PPA (performance, power, area), and yield while adhering to strict foundry rules. Key Responsibilities: - Lead end-to-end layout design and floorplanning for advanced-node memory IPs. - Deliver DRC/LVS/DFM-clean GDS with robust EM/IR reliability sign-off. - Collaborate with circuit, CAD, and SoC integration teams for optimal implementation. - Innovate layout techniques to achieve competitive density and performance targets. - Provide comprehensive IP deliverables: GDSII, LEF, Liberty (.lib), Verilog models, and integration documentation. Success Metrics: - Achieve world-class memory density and access times. - Meet or exceed power and yield requirements across PVT corners. - Enable seamless integration into customer SoCs.,

More Jobs at M31 Technology

Memory layout design lead

karnataka

5.0 - 9.0 yrs

Salary: Not disclosed

Memory layout design lead

karnataka

5.0 - 9.0 yrs

Salary: Not disclosed

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Memory layout design lead