6 Lef Jobs

Job Description You will be responsible for leveraging your Credit Risk knowledge and hands-on experience in Credit Risk reporting like LEF, SCCL, along with a deep understanding of AIRB/FIRB models. Your role will involve IT BA experience, hands-on SQL, Agile project execution, and excellent presentation and communication skills. Key Responsibilities: - Utilize your expertise in Credit Risk models (LGD, PD, EAD) to enhance credit risk reporting and regulatory compliance - Collaborate with stakeholders, product owners, and technology teams to design and deliver innovative solutions - Demonstrate hands-on experience with LEF and SCCL reporting - Ensure a solid understanding of AIRB/FIRB frame...

As an Analog Mixed Signal Designer at ARF Design, you will be responsible for working on the design of building blocks used in high-speed IPs such as DDR, LPDDR, HBM, UCIe, and PCIe. Your primary responsibilities will include: - Deriving circuit block level specifications from top-level specifications - Conducting optimized transistor-level design of analog and custom digital blocks - Performing Spice simulations to cover detailed specifications - Guiding layout design for best performance, matching, and power delivery - Characterizing the performance of designs in PVT + mismatch corners, including reliability checks - Generating and delivering behavioral (Verilog), timing (lib), and physica...

As a Memory Layout Lead at our company, you will play a crucial role in driving the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs including SRAM, ROM, register files, CAMs, and more. Your main responsibility will be to lead the end-to-end layout design and floorplanning for advanced-node memory IPs. Additionally, you will collaborate with circuit, CAD, and SoC integration teams to ensure optimal implementation. Your innovative layout techniques will be essential in achieving competitive density and performance targets. You will also be responsible for providing comprehensive IP deliverables such as GDSII, LEF, Liberty (.lib), Verilog m...

Job Overview The successful candidate will work on Characterization, CAD views generation and Packaging of General purpose and Specialty IOs. The candidate is expected to generate and validate EDA views like .lib (NLDM/NLPM, CCST/P/N, variation modelling etc), APL, CMM, BPA, Verilog, ATPG, NDM, LEF, IBIS, CDL, GDS etc. The candidate will also be required to work on scripting to optimize above activities. The candidate will also be required to work on flow and methodology setup for these EDA views. Responsibilities and Duties Generation, validation, QA and release of IO libraries Ensure high quality and timely deliverables Interacts with Design and layout teams to understand the design and fl...

The successful candidate will be responsible for Characterization, CAD views generation, and Packaging of General purpose and Specialty IOs. You will independently drive the generation and validation methodologies for various views including .lib (NLDM/NLPM, CCST/P/N, variation modeling, etc.), APL, CMM, BPA, Verilog, ATPG, NDM, LEF, IBIS, among others. In addition to this, you will create, validate, and release these IP packets ensuring timeliness and highest quality. Furthermore, mentoring team members on different flows and methodologies will be part of your responsibilities. Your main tasks and duties will include setting up the generation and validation flow methodologies for different ...

What You ll Need: BTech/MTech in a relevant field. 8+ years of relevant experience and team management skills. Ability to lead projects with high product quality and efficiency. In-depth understanding of deep submicron effects, floorplan techniques in advanced process technologies. Proficiency in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame, and pitch requirements. Scripting skills for layout automation (a plus). Excellent written and verbal communication skills.