Emulation Engineer

0 years

0 Lacs

Posted:18 hours ago| Platform: Linkedin logo

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Work Mode

Remote

Job Type

Full Time

Job Description

Job Details

Job Description:
  • Builds emulation models and solutions from RTL design using synthesis, partitioning, and routing tools.
  • Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
  • Enables acceleration of RTL development and improve emulation model usability for presilicon verification, postsilicon validation, and software development.
  • Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
  • Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
  • Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

Qualifications

  • B.Tech /M.Tech degree in Electrical Engineering, Electrical and communication Computer Science and.
  • Should have 4-12 yrs of experience.
  • Emulation experience is mandatory.
  • Experience in Verification planning.
  • Experience in Verification testcase development.
  • Experience in RTL code debug [Verilog preferred]
  • Experience in Post Silicon debug support
  • Programming skills: Python, C/C++, Perspec, Verilog
  • Good multi-tasking skills-Team-player, great communication skills

Preferred:

  • Experience in Pre-Si power and performance correlation.
  • Familiarity with System level emulation-based verification.
  • Familiarity with Synopsys tools
  • Familiarity with Post-Si Validation and debug support
  • Familiarity with Assembly, System Verilog
  • Programming exposure with virtual platforms
  • Familiarity of Intel CPU architecture or x86 architecture in general
  • Experience in emulation with Zebu or Haps, SLE environment

Job Type

Experienced Hire

Shift

Shift 1 (India)Primary Location:Virtual IndiaAdditional Locations:

Business Group

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.

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