Staff Engineer, ASIC Development Engineering

Experience in ASIC verification, Expertise in System Verilog and UVM, Verilog.

Experience in IP level verification, testbench architecture development, Testbench component developments. Expertise in coverage closer, code coverage, functional coverage Experience in Gate level simulations.

The candidate should be able to define verification plan, create testbenches, testcases,gate level simulations etc independently.

Knowledge on serial protocols UFS, PCIe, USB, MIPI or any other serial protocol. Knowledge on memory protocols - SD, eMMC, Flash etc.

Knowledge on scripting languages like Python, Perl etc.

Keen on continuous process improvement to improve Quality and time

Qualifications

• Bachelors or Masters degree in Electrical/Electronic Engineering or a related field
• 4-8 years of experience in digital design, with a strong focus on RTL design and integration for complex SoCs
• Expert-level proficiency in Verilog/SystemVerilog
• Deep understanding of AMBA protocols (AXI/AHB/APB), interconnects, and peripherals