Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 10+ Years. Location: Vizag or Bangalore. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions. Key Responsibilities: Define and develop microarchitecture specifications for complex SoC designs. Lead RTL design and implementation using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA). Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution. Perform design trade-off analysis to meet functional, performance, and power requirements. Develop and implement design methodologies to improve efficiency and quality. Mentor and guide junior engineers, fostering a culture of innovation and excellence. Participate in design reviews, provide technical leadership, and ensure adherence to project timelines. Qualifications: 10+ years of hands-on experience in RTL design and microarchitecture development. Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis . Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems . Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization). Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning). Strong scripting skills in Tcl, Python, or Perl for automation and flow development. Excellent problem-solving skills and attention to detail. Strong communication and leadership skills. What We Offer: Opportunity to work on cutting-edge semiconductor designs and innovative technologies. Collaborative and inclusive work environment. Competitive compensation and benefits package. Professional growth and development opportunities. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design Show more Show less

Eximietas Hiring Senior Design Verification Engineers/Leads Experience - 5-15 Yrs. Location - Visakhapatnam Job Description: Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. Develop and implement comprehensive verification strategies , including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM ). Conduct Gate-level simulations and power-aware verification using tools like Xprop and UPF . Collaborate closely with cross-functional teams, including architects, designers , and pre/post-silicon verification teams , to ensure alignment and seamless integration of verification efforts. Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality. Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance. Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment . Ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines . Uphold quality standards and implement best test practices , contributing to continuous improvements in verification methodologies. Work with verification tools from Synopsys and Cadence , including VCS and Xsim . Integrate third-party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage. Qualifications: 5+ years of hands-on experience in SoC Design Verification . Expertise in verification of high-speed SoCs and various protocols, including I2C/I3C , SPI , UART , GPIO , QSPI , PCIe , Ethernet , CXL , MIPI , DDR , and HBM . Proficiency in System Verilog for verification, including assertions and coverage . Experience with gate-level simulations and power-aware verification using Xprop and UPF . Strong hands-on experience with VCS and Xsim from Synopsys and Cadence . Mentorship experience, providing guidance to junior engineers and managing verification teams. Demonstrated ability to work with cross-functional teams , ensuring effective collaboration and verification signoff. Strong understanding of verification methodologies and ability to contribute to their continuous improvement. Show more Show less

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less

We are looking for experienced Senior/Lead ASIC Verification Engineers for our Noida-VIP team. Does this sound like a good role for you? Experience : 5yrs to 15 years (multiple roles) Location: Noida Associated with Verification especially using industry-standard protocols & methodology Languages: Hands-on experience with System Verilog & Verilog . Should have a good understanding of Object Oriented Programming. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies . Protocol experience: Should have experience on any of the UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Please share your updated CV to taufiq@synopsys.com or refer who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Show more Show less

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, Experience Level: 5-15 years Education Requirements: B.Tech/M.Tech in ECE, EEE Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Analytical debugging skills Knowledge on C Based Testcases Knowledge of SoC,Memory and Cache Architectures Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One Scripting languages like Make flow, Perl ,shell, python - Any One ASIC RTL Engineer Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols PCIe DDR Ethernet I2C, UART, SPI Expertise in setting up and using tools like Spyglass Lint/CDC Synopsys DC Verdi/Xcellium Understanding of scripting languages like Make flow, Perl ,shell, python etc Understanding of processor architecture and/or ARM debug architecture is a plus Able to help and debug issues for multiple subsystems Able to create/review design documents for multiple subsystems Able to support physical design, verification, DFT and SW teams on design queries and reviews. Show more Show less

Designation: Technical Support Engineer - VLSI Experience : 0-1 Years Education : B.tech/ BE- or M.Tech VLSI. ECE/ Diploma in Mechatronics/ECE Industry Type: Education / E-Learning / Semiconductor Category: Technical Job Description Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Desired Candidate Profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. For more details, kindly contact 7406043555, fiza@maven-silicon.com

1.Must Have: SoC or IP 2.Experience Languages : System Verilog (must) 3.Methodologies: OVM/UVM/VMM 4.Protocols:DDR/USB/Ethernet/PCIE/Video/HDMI/MIPI/DSI/CSI 5.Processor/ARM Based SoC Verification experience 6.Candidate must have expertise in System Verilog. 7.Experience in ARM base SoC Verification 8.Strong Analytical skills desirable if having worked.

Summary Established in 2001, EnSilica is a publicly listed company (LON:ENSI), designing industry leading, application specific integrated circuit chips (ASIC), for customers ranging from start-ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. With its head office on Milton Park, Oxfordshire, and other offices in Bristol, Sheffield, Brazil (Porto Alegre) and India (Bangalore), EnSilica currently employs more than 160 people. We are looking for a very experienced verification engineer who can not only strengthen the team through their technical expertise but also bring leadership and grow the verification business within EnSilica. You will have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly assimilate the verification challenge and help define an effective and pragmatic verification strategy and gain the support of the end-customer for the chosen approach. You will need to understand the importance of monitoring key metrics to assess progress and predict the end-point for the verification process. Responsibilities Verification specialist working on customer and internal projects often as the verification lead. Provide high-class verification support to a wide range of projects using a range of advanced verification techniques including constrained random, coverage driven, assertion-based and formal methods. You would also be responsible for the development of a comprehensive verification strategy and plan, along with the architecting and development of the complete test environment. Active participation in the verification community to drive the introduction of new and effective techniques within our business to help solve the verification challenges faced by our customers. Close working with our customers to build a strong relationship that results in repeat business. Education / Key Skills / Experience BE/ME in Electronics /Computer Science 1 group University. 15+ years experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the EnSilica one toward continuous improvement Ideally you will be familiar with both Mentor Questa and Cadence Incisive tool and ideally some exposure to low power verification using UPF based flows A good understanding of functional safety and quality processes, to achieve ISO26262 or similar standards compliances will be considered as a strong plus Personality Excellent communication and interpersonal skills. Strong and effective presentation skills, able to operate at multiple levels including senior management. Self-motivated achiever who gains satisfaction from providing excellent customer service and has a can-do attitude. Happy to take ownership of problems and provide suitable solutions. Creative problem solving. Team player. Ability to work in a dynamic environment.

This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 15+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.

The Opportunity Were looking for the Wavemakers of tomorrow. What You ll Do SERDES sub-block design and technical leadership for clocking, TX, RX etc Define Block-level architecture and circuit topologies to meet system spec Circuit Design and simulation across PVT and sign off quality matrix to meet specs Mentor the junior designers and support them in problem solving Support .lib generation and Verilog modelling for block owned and validate with schematic Custom Layout guidelines and post-layout simulations Documentation, Review and Signoff on design What You ll Need Minimum 8+ years of experience in Analog circuit design from a reputed product-based company Previous experience of leading analog engineering design teams is must Experience in dual patterning FinFET design in in TSMC 3nm, 5nm etc Experience designing circuit at 56+ Gbps speed Understanding of device basics and physics High-speed Driver and Receiver designs, PLL design with solid system understanding BTech/MTech/MS in VLSI from a reputed university "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Position: Design Verification Engineer Location: Bangalore Experience: 5+ Years Key Skills Required: Strong experience in CXL or PCIe Protocol Verification Proficiency in UVM, SystemVerilog, Verilog Hands-on experience with simulation tools (VCS, ModelSim, Questa, etc.) Excellent debugging and problem-solving skills Good to Have: Exposure to AMBA protocols (AXI, AHB, APB) Knowledge of scripting languages like Python or Perl Educational Qualification: Bachelor s or Master s degree in Electronics Engineering , Electrical Engineering , or related field

Alphawave Semi is looking for Senior Engineer I - ASIC Design to join our dynamic team and embark on a rewarding career journey. Analyze and assess problems. Apply quality principles and methodology in processes to enhance output. Assess new product designs to meet project and product requirements. Create engineering designs. Identify the design needs of clients. Manage disputes and conflicts. Manage product design and development to meet project and product requirements. Oversee Workplace Safety and Health Systems (WSH) for the company.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. GCS AE Job Description Document Job Title: Lead Application Engineer - GCS Location: Bangalore / Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture builds and fosters diversity, equity and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary As a member of the GCS Organization for the MSA (Multiphysics System Analysis), you will partner with world-wide Cadence customers to provide post sales technical consultation for IC level Power System analysis products for implementing cutting-edge designs. This involves working closely with the customers to understand and debug complex issues enabling them to proceed further with design cycle phases, help them leverage the latest tool capabilities, and guide them with implementation of software in their design methodologies. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest design practices in industry and demonstrate expertise by authoring high impact knowledge content. This role also provides opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to identify and prioritize the product improvement initiatives with your timely feedback and observations. This an excellent opportunity to work in a supportive, flexible and friendly work environment that GCS offers, where we are vested in each other’s success, and are passionate about technology and innovation. Job Responsibilities Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset of Cadence products with focus on productivity, and customer satisfaction Support multiple tools/methods for customer requiring general domain knowledge and developing business experience Assist in creation of high quality and impactful knowledge content in MSA domain Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements Work on problems of moderate scope that may require analysis of situations, data or tool problems Qualifications Bachelor’s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience OR Masters with 3-4 years of related experience OR PhD with 1 years of related experience Experience And Technical Skills Required 3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design Debugging of Low power and multiple power domain analysis for chip power integrity sign-off. Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal); knowledgeable of at least 50% of a given flow; detailed knowledge in one CDN tool, learning others; ability to analyze customer's environment and evaluate appropriate support solutions; learning competitive tools/technologies Must have excellent debugging skills and ability to separate out the critical issues from trivial ones. Ability to solve interface level problems emanating from IC Implementation side and System analysis side. Ability to debug Timing and thermal issues in relation to IR and EM is a plus Good understanding of Hardware description languages like VHDL, Verilog, System Verilog. Knowledge on TCL, Perl or Python scripting. Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What Makes You Eligible An accomplished leader with a minimum of 8+ years of experience in software design & development and a Bachelor's / Masters degree Excellent communication skills (written/verbal) & Team spirit Risk taker with passion for innovation Autonomous working to explore new technologies

Outlier helps the world’s most innovative companies improve their AI models by providing human feedback. Are you an experienced software engineer who would like to lend your coding expertise to train AI models? We partner with organizations to train AI large language models, helping cutting-edge generative AI models write better code. Projects typically include discrete, highly variable problems that involve engaging with these models as they learn to code. There is no requirement for previous AI experience. About The Opportunity Outlier is looking for talented coders to help train generative artificial intelligence models This freelance opportunity is remote and hours are flexible, so you can work whenever is best for you You may contribute your expertise by… Crafting and answering questions related to computer science in order to help train AI models Evaluating and ranking code generated by AI models Examples Of Desirable Expertise Currently enrolled in or completed a bachelor's degree or higher in computer science at a selective institution Proficiency working with one or more of the the following languages: Java, Python, JavaScript / TypeScript, C++, Swift, and Verilog Excellent attention to detail, including grammar, punctuation, and style guidelines Payment Currently, pay rates for core project work by coding experts range from USD $13.50 to $27.50 per hour. Rates vary based on expertise, skills assessment, location, project need, and other factors. For example, higher rates may be offered to PhDs. For non-core work, such as during initial project onboarding or project overtime phases, lower rates may apply. Certain projects offer incentive payments. Please review the payment terms for each project. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification. Required Experience Strong background on functional verification fundamentals, environment planning, test plan generation, environment development System Verilog experience and experience with UVM based functional verification environment development is required. Good knowledge of verilog/vhdl/C/C++/Perl/Python. Expertise in AMBA protocols. (AXI/AHB/APB). Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols Good handle on using one or more version control software Good handle on using one or more load sharing software Desirable Skills And Experience Prior experience with Cadence tools and flows is highly desirable. Familiarity with ARM/CPU architectures is a plus. Experience in developing c-based test cases for SOC verification Some experience with assembly language programming Good knowledge of some of the protocols like UART, I2C, SPI, JTAG Embedded C code development and debug Formal Verification experience Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description RTL Design Engineer for DDR Memory Controller IP development team. The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4. The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines. Position Requirements BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. RTL Design using Verilog is a must. System Verilog experience and experience with UVM based environment usage / debugging is required. AXI3/4 experience is desired. DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must. Prior experience in IP development teams would be an added advantage. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Product Validation Engineer II Location: Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary And Responsibilities This position involves validation of Cadence Perspec System Verifier tool. Work closely with Product Engineers and R&D on understanding feature requirements. Based on feature requirements, develop test plan, and create tests in PSS. Perform unit, integration, and solutions level validation. Develop & maintain regression system. Job Technical Requirements 2 to 5 years of experience in Verification Good Understanding of various verification concepts such as Verification architecture, coverage, checkers, test plan etc. Good scripting knowledge (Perl/Python) is an advantage. Good understanding of HDL (Verilog and SV) is an advantage. Knowledge of PSS would be a strong plus. Qualifications BE/BTech/ME/MS/MTech in Software/Computer Engineering Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

Outlier helps the world’s most innovative companies improve their AI models by providing human feedback. Are you an experienced software engineer who would like to lend your coding expertise to train AI models? We partner with organizations to train AI large language models, helping cutting-edge generative AI models write better code. Projects typically include discrete, highly variable problems that involve engaging with these models as they learn to code. There is no requirement for previous AI experience. About The Opportunity Outlier is looking for talented coders to help train generative artificial intelligence models This freelance opportunity is remote and hours are flexible, so you can work whenever is best for you You may contribute your expertise by… Crafting and answering questions related to computer science in order to help train AI models Evaluating and ranking code generated by AI models Examples Of Desirable Expertise Currently enrolled in or completed a bachelor's degree or higher in computer science at a selective institution Proficiency working with one or more of the the following languages: Java, Python, JavaScript / TypeScript, C++, Swift, and Verilog Excellent attention to detail, including grammar, punctuation, and style guidelines Payment Currently, pay rates for core project work by coding experts range from USD $13.50 to $27.50 per hour. Rates vary based on expertise, skills assessment, location, project need, and other factors. For example, higher rates may be offered to PhDs. For non-core work, such as during initial project onboarding or project overtime phases, lower rates may apply. Certain projects offer incentive payments. Please review the payment terms for each project. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in UCIe domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a UCIe VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members ( RnD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Experience and Technical Skills required (edit as per the requirement): At least 5 to 8 years of experience with Verification and Design Working knowledge with UCIe domain and functional verification. Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics/Computer Science or equivalent Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

Hiring for Freshers Desingnation:- Technical Support Engineer - VLSI Work Mode: WFO (6 days) No.of positions: 10 Experience: 0 - 1 years Education: BE/BTech/MTech/ECE/EEE in VLSI Industry Type: Education / E-Learning / Semiconductor Filter: Full- time- Work from Office Stipend: 15k - 20k Role & responsibilities Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics.

RoleFront-End RTL Design Automation Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

RoleSenior CAD Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a Senior CAD Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less