2321 Verilog Jobs - Page 28

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive of the micro-architecture, and also help with architecture/product definition through early involvement in the product life-cycle. Roles And Responsibilities Performance exploration. Explore high performance strategies working with the CPU modeling team. Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals. Functional verification support. Help the design verification team execute on the functional verification strategy. Performance verification support. Help verify that the RTL design meets the performance goals. Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and po Preferred Qualifications Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high performance techniques and trade-offs in a CPU microarchitecture Experience using a scripting language such as Perl or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 15+ years of Hardware Engineering or related work experience. 4+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 4+ years of experience utilizing schematic capture and circuit stimulation software. 4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 4+ years in a technical leadership role with or without direct reports. Principal Duties And Responsibilities: Leverages expert Hardware knowledge and experience to plan, optimize, verify, and test highly critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Drives the development of design rules and processes for electronic hardware, equipment, and/or integrated circuitry. Serves as an expert resource for conducting highly complex simulations and analyses of designs as well as for the implementation of designs with the best power, performance, and area. Collaborates with high-level representatives across functions (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement and drive new requirements and the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing solutions for leading edge products in highly advanced processes and bring-up product to meet customer expectations and schedules. Serves as an expert resource for the evaluation of reliability for highly critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Advises multiple teams of engineers in the development of complex hardware designs, evaluating various design features to identify potential flaws or issues. Writes detailed technical documentation for highly complex Hardware projects; reviews technical documentation for experienced engineers. Level Of Responsibility: Provides supervision to direct reports. Decision-making is critical in nature and highly impacts program, product, or project success. Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents. Works within the prescribed budgetary objectives of the department. Has a great degree of influence over key organizational decisions. Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069277

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069772

SOC RTL Design Verification Experience : 4 to 10 Years Location : Bangalore Key Responsibilities: • Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verification • Development and verification of post-si validation sequences using C/C++ • Create methodology-based (UVM) verification testbenches and components from scratch at SOC level along with re-usability of IP level components. • Experienced with Verilog, System Verilog, and C or C++ • Good understanding of JTAG protocol • Contributes to test plan development. Candidate past experience requirements, • Should have experience in system-level Verification. • DDR prior experience is not mandatory. About Company: ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

Hi All, Lead RTL Design Engineers Experience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and Bangalore Basic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification, design, user-guide, Interface specification, etc., o Experience:  Experience in documenting, designing, implementing complex designs Experience in designing HW/SW interfaces  Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools  Experience with RTL design of Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc.  Excellent ability to analyze and isolate RTL and test bench issues, RTL and SW issues  Experience in understanding of software and designing HW interfaces for software  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Regards, K Himabindu Mail ID: himabindu.jeevarathnam@acldigital.com

Principal RTL Design Engineer & Architect Bangalore We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in leading state of the RTL designs involving solutions for automotive camera and display systems. Responsibilities • Design and develop microarchitectures for a set of chips involving MIPI CSI,DSI and SerDes protocols • Microarchitecture and RTL coding ensuring optimal performance, power, area • Collaborate with software teams to define configuration requirements, verification collaterals etc. • Work with verification teams on assertions, test plans, debug, coverage etc. Qualifications and Preferred Skills • BTech, MTech in ECE/EE • 10+ years hands-on experience in microarchitecture and RTL development • Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface • In-depth understanding of MIPI CSI and DSI protocols • Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog • Familiarity with industry-standard EDA tools and methodologies • Experience with large high-speed, pipelined, and low power designs • Excellent problem-solving skills and attention to detail • Strong communication and collaboration skills • Experience with modern programming languages like Python is a plus

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities : Design : Participate in the design of CPU subsystems, collaborating with architects and design engineers. Contribute to micro-architectural decisions, considering performance, power, and area trade-offs. Develop detailed design documents and schematics for assigned subsystems. Verification : Develop comprehensive test plans and verification strategies for assigned subsystems. Create and implement SystemVerilog/UVM testbenches, checkers, and coverage groups. Execute verification plans, analyse results, and debug failures effectively. Work closely with verification engineers and architects to identify and resolve issues. Additional Responsibilities: Stay up-to-date on the latest advancements in CPU architecture and verification methodologies. Contribute to technical discussions and actively participate in design reviews. Collaborate effectively with cross-functional teams to achieve project goals. Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 3-5 years of experience in CPU design or verification. Strong understanding of digital design principles, RTL, and verification methodologies (UVM, SystemVerilog). Experience with Verilog/SystemVerilog coding and debugging. Familiarity with CPU microarchitecture concepts and verification best practices. Excellent analytical and problem-solving skills. Strong communication and collaboration skills. Ability to work independently and as part of a team. Benefits : Competitive salary and benefits package. Opportunity to work on cutting-edge technology and make a real impact. Regards, K Himabindu Mail Id: himabindu.jeevarathnam@acldigital.com

Hi All, ACL Digital is hiring #Senior #Design #Verification Engineer! Experience: 4 Years Location: Bangalore / Hyderabad Notice Period: Immediate to 30 Days Preferred! We're seeking experienced professionals ASIC/SoC verification. If you have expertise in UVM/System Verilog, proficiency in scripting languages like Python/Perl/TCL, and a strong grasp of protocols such as AXI, APB, PCIe, and DDR. Thanks, K Himabindu

Hi Folks ACL Digital is Hiring! Experience: 4 - 5+ Years Location: Bangalore / Hyderabad Looking: Immediate to 20 days Hiring | RTL Design Engineer Strong experience in RTL Design using Verilog/System Verilog Exposure to complex SoC/ASIC design and integration Hands-on with synthesis, Lint, CDC preferred Share resume at himabindu.jeevarathnam@acldigital.com #RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog #SoC Thanks, K Himabindu

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: SOC NLP & Power Management): Work on SOC level verification activities, the person will be responsible for bringup of UPF simulation at SOC. Work with testbench team to bringup NLP (UPF) simulation, debug simulation issues. He will be responsible to coordinate with Design team for UPF delivery, work with design (IP, Subsystem, SOC) for quality UPF delivery and resolve issues. He should have good understanding of power architecture and UPF’s He will be responsible to create TB collaterals for NLP simulation bringup. The Person Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for SOC testbench, Power management, UPF, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions. Key Responsibilities NLP Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team) Power verification is key responsibility. Work with power architects to resolve issues seen in simulation. Preferred Experience Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. NLP Simulation is must requirement. Strong hands-on experience in different SOC Verification activities, NLP Simulation, Power verification, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. Academic Credentials BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-8 years of strong DV experience in NLP simulation, IP, Sub System & SOC Verification, Power management verification Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

As a member of AMD's CPU Performance Validation team in Bangalore, you will play a crucial role in the design of next-generation AMD CPUs. Your responsibilities will include gaining a deep understanding of AMD X86 CPU architecture and microarchitecture, debugging performance issues in RTL, and providing feedback to the design team for the latest CPU generation in pre-silicon and emulation environments. We are looking for individuals with a creative mindset and a natural inclination to delve into details. This team is ideal for those who can grasp the present while envisioning the future. If you are someone who is willing to go the extra mile to refine existing processes and possesses innovative ideas waiting to be realized, this is the perfect opportunity for you. Your success in this role will be supported by excellent interpersonal and communication skills, along with the ability to thrive in a fast-paced and dynamic environment. Continuous learning is essential in this ever-evolving industry, and as such, self-improvement and skill enhancement are highly valued traits. Collaboration, learning, and sharing knowledge within the team are pivotal to our collective growth and success. Key Responsibilities: - Building infrastructure for performance verification and assessing X86 processor performance - Developing targeted tests to evaluate processor performance - Debugging failures in simulation and emulation environments - Writing automatized triages and creating tools using Perl/Ruby or C++ to streamline functional debugging processes - Participating in post-Si bug recreation activities as needed Preferred Experience: - 3-15 years of experience in processor/ASIC performance correlation - Expertise in micro-architecture testing for modern high-performance processors - Proficiency in writing tests and developing infrastructure to test modern processor performance - Skills in programming and scripting languages such as C, C++, Perl, and Python - Strong background in Digital Design, RTL design, model performance improvement, and Processor Architecture - Prior experience in performance correlation of Processor subsystems is advantageous - Comprehensive understanding of computer architecture through relevant research, projects, or industry exposure - Proficiency in programming languages like C/C++ and assembly - Basic knowledge of Verilog Academic Credentials: - Bachelors/Masters in Computer Science, Electrical, or Electronics Engineering with relevant coursework and research projects Join us at AMD, where we are dedicated to transforming lives through technology and creating innovative computing experiences for the future. If you are ready to contribute to our mission and be part of a collaborative and forward-thinking team, we invite you to advance with us.,

As an Engineer at our company, you will be involved in the design and development of applications for FPGA target platforms. We are seeking individuals with proficiency in programming languages such as VHDL or Verilog and Matlab, specifically to work on FPGA platforms for communication protocol and algorithm development. Your primary responsibilities will include designing, developing, and debugging VHDL or Verilog based systems, while possessing a strong understanding of the FPGA platform development lifecycle. The ideal candidate should have practical experience in FPGA-based system design and development. This is a full-time position.,

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Job Description Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076998

Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as we'll as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. Desired Skills & Experience: Experience level 5 to 10 years. Strong domain knowledge on one or more - PCIe, USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB) Should have worked on SOC Level / IP Level design using VHDL, Verilog coding RTL Coding, CDC, Lint, Spyglass. Good in logic design. Expertise in Verilog and / or VHDL is desired. Strong in SV & OOPS IP or SoC verification Functional + code coverage ARM based SoC verification Capable of developing C tests Working knowledge SV/METH Code coverage Education: B. Tech/B. E. , in Electronics/Telecommunication, Electrical) OR (PG - M. Tech/M. E, in (Electrical, Electronics/Telecommunication)

Design, simulate, and verify transistor-level analog circuits for Phase-Locked Loops (PLLs), including key blocks such as VCOs, charge pumps, loop filters, and phase/frequency detectors. Collaborate with cross-functional teams to integrate PLLs into advanced semiconductor products and ensure high performance and reliability. Key Responsibilities: - Design and develop analog PLL circuits at the transistor level, focusing on VCOs, charge pumps, loop filters, and phase/frequency detectors. - Use CADENCE simulation tools, MATLAB for circuit design, modeling, and verification. - Perform circuit simulations to validate functionality, performance, and reliability; optimize designs based on simulation and test results. - Collaborate with layout engineers to ensure robust physical design, addressing parasitics, noise, and signal integrity. - Develop and execute test plans for prototype validation; analyze test data and iterate on designs as needed. - Document design specifications, schematics, simulation results, and test reports; participate in design reviews. Qualifications: - Bachelor or Master degree in Electrical Engineering or related field. - Strong understanding of analog and mixed-signal circuit design, with direct experience in PLL architectures and transistor-level design. - Excellent problem-solving, documentation, and communication skills. - 3+ years of relevant experience preferred; advanced degrees or additional experience are advantageous. Preferred Skills: - Experience with high-frequency PLLs (e. g. , > 10GHz), spread-spectrum clocks, or advanced CMOS/FinFET processes[2][3]. - Familiarity with digital design tools (e. g. , Verilog) and mixed-signal integration[2][3]. - Project management and mentoring abilities are a plus[3]. Role: Design, simulate, and verify transistor-level analog circuits for Phase-Locked Loops (PLLs), including key blocks such as VCOs, charge pumps, loop filters, and phase/frequency detectors. Collaborate with cross-functional teams to integrate PLLs into advanced semiconductor products and ensure high performance and reliability. Key Responsibilities: - Design and develop analog PLL circuits at the transistor level, focusing on VCOs, charge pumps, loop filters, and phase/frequency detectors. - Use CADENCE simulation tools, MATLAB for circuit design, modeling, and verification. - Perform circuit simulations to validate functionality, performance, and reliability; optimize designs based on simulation and test results. - Collaborate with layout engineers to ensure robust physical design, addressing parasitics, noise, and signal integrity. - Develop and execute test plans for prototype validation; analyze test data and iterate on designs as needed. - Document design specifications, schematics, simulation results, and test reports; participate in design reviews. Qualifications: - Bachelor or Master degree in Electrical Engineering or related field. - Strong understanding of analog and mixed-signal circuit design, with direct experience in PLL architectures and transistor-level design. - Excellent problem-solving, documentation, and communication skills. - 3+ years of relevant experience preferred; advanced degrees or additional experience are advantageous. Preferred Skills: - Experience with high-frequency PLLs (e. g. , > 10GHz), spread-spectrum clocks, or advanced CMOS/FinFET processes[2][3]. - Familiarity with digital design tools (e. g. , Verilog) and mixed-signal integration[2][3]. - Project management and mentoring abilities are a plus[3].

Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies. Prepare basic documentation and status reports as required. Bachelor degree in Electronics, Electrical, or related field. Basic understanding of digital design and DFT concepts. Familiarity with Verilog or VHDL is an advantage. Good analytical and communication skills Work Experience Assist in Design for Testability (DFT) activities for VLSI chip designs. Support scan insertion, ATPG pattern generation, and simulation tasks. Work with senior engineers to validate test coverage and resolve issues. Learn and apply industry-standard DFT tools and methodologies.

CPU Verification Manager Fortune 100 Organization Location: Bangalore As a Hardware Developer , you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable our customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role And Responsibilities As a Functional verification engineer, you will be working on server processors/SOC or ASICs used in servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in Functional verification tools and methodologies. Owning and Driving execution of subunits/unit level Verification Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Work with Verification community to improve Verification methodology. Preferred Education Master's Degree Required Technical And Professional Expertise 12 + years of experience in Functional Verification of processors or ASICs. Minimum 9+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading teams Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred Technical And Professional Experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Good understanding of the Server System Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and firmware scenarios in RTL and GLS. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Mentor junior verification engineers and review their work. Establish verification methodologies and best practices QUALIFICATIONS Minimum requirements: Minimum of 3-4 years of experience in Digital IP Sub-system/SOC DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Experience in one or many of the following: C based Digital DV, scripting (Python/Perl/Shell) knowledge, UVM/System Verilog, AMS/GLS/CPF/UPF based verification, Post silicon verification etc Preferred qualifications: Strong in digital design fundamentals, computer organization & architectures and bus protocols. A good understanding of analog functionality and exposure to analog IC design methods. Ability to solve problems using a systematic approach Excellent debugging skills with Verilog/VHDL designs Work experience on C based environment with ARM/DSP processor-based systems including power aware simulations is a plus. Experience in Motor control/ BLDC motor driver devices including commutation, sensorless control and feedback systems are an added advantage Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Effective communication skills to interact seamlessly with all stakeholders Ability to quickly ramp on new systems and processes Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. JOB INFO Job Identification 25002354 Job Category Engineering - Product Dev Posting Date 07/11/2025, 09:22 AM Degree Level Bachelor's Degree Locations BANG Bagmane Tech Park, Bangalore, 560093, IN ECL/GTC Required Yes

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid