RoleASIC CAD Lead Engineer Experience10+years LocationBangalore Notice PeriodMax 15days preferred Role Overview We are looking for a ASIC CAD Lead Engineer to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What You'll Do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What You Need To Have Tech/B 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks Show more Show less

3 years Service Agreement - Freshers Role & responsibilities: Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Preferred candidate profile Freshers Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. 3 years Service Agreement.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in UCIe domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a UCIe VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members ( RnD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Experience and Technical Skills required (edit as per the requirement): At least 5 to 8 years of experience with Verification and Design Working knowledge with UCIe domain and functional verification. Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics/Computer Science or equivalent Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

About Marvell . Your Team, Your Impact This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 10+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075701 Show more Show less

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view! We are not looking for superheroes, just super minds We seek a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with 4-8 years of significant experience in software development. Experience in EDA will be a plus! Proficiency in C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Your understanding of HDL languages – Verilog/VHDL/System Verilog is essential. We value your knowledge of scripting languages, hands-on knowledge of Revision control systems like Perforce will only improve the development time. Good analytical, abstraction and interpersonal skills will help in creating bigger and sustainable solutions for complex systems. Ability to work with multi-functional teams as a great teammate will help in creating good solutions that resolve actual customer issues. Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Teammate and good management skills We've got a lot to offer, how about you? We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform everyday Show more Show less

Over 5 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Over 8 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Over 10 years of digital IP verification, advanced knowledge of ASIC/SOC Design flow and state of the art verification flow Proficient with Verilog, System Verilog and UVM. · Good in UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) · Good in defining and developing UVM based verification frameworks, testbenches, processes and flows. · Good in working in Linux and Windows environments. · Familiarity with power aware simulation and firmware/hardware co-verification is a plus. · Familiarity with industry standard high-speed protocols such as USB, PCIE, UFS, SATA, Ethernet is a plus. · Familiarity with industry standard interconnects such as AMBA (AXI, APB, AHB) is a plus. Show more Show less

Become a Pioneer in Computing - Join Vicharak! At Vicharak , we stand at the vanguard of a computing revolution. Similar to the trailblazers at Bell Labs in 1947 who witnessed the birth of the transistor, we're revolutionizing the future of semiconductors through innovative FPGA technology. Unlike traditional processors, our FPGAs enable programmable changes in inner circuitry, unlocking new dimensions in parallelism, speed, and computing. Our groundbreaking VAAMAN hardware system, combining FPGA and SBC, epitomizes our innovation, and we're searching for talented individuals who share our fervor for this field. We invite researchers, developers, designers, engineers, and architects to join us in crafting the next era of computing. What You'll Learn: Software languages: C/C++, Python, HDL languages like Verilog and System Verilog. Utilize diverse tools, including compilers such as GCC and X86s, alongside IDEs like Visual Studio and PlatformIO. Master FPGA tools like Vivado, Radiant, and Efinix FPGAs. Develop adaptable skills to tackle challenges effectively and gain insights spanning from keyboards to complex servers. What You'll Work On: Engage in our thrilling projects, delving into various facets of our Acceleration framework encompassing AI Acceleration, Software Acceleration, and optimizing peripherals. Gain hands-on experience in Verilog and System Verilog, mastering the fundamentals of these languages. Join Us at Vicharak - Shape the Future of Computing! If you possess an unwavering interest in this field and an insatiable thirst for knowledge, we want to hear from you! Come be part of Vicharak and be at the forefront of molding the future of computing through our groundbreaking FPGA technology. For more insights, visit our website: https://vicharak.in Show more Show less

SENIOR LOGIC DESIGN ENGINEER Fortune 100 Organization Location: Bangalore Title Logic Design Engineer Your Role and Responsibilities As a Logic Design Engineer, you will play a pivotal role in the end-to-end development of features with significant impact on our Mainframe and/or Power customers. From conceptualization to validation, you will be responsible for developing features, presenting proposed architectures, estimating efforts, and collaborating across various teams to ensure successful implementation. Your primary responsibilities include: Feature Development and Architecture: Develop features and propose architectures in high-level design discussions, ensuring alignment with project goals and customer requirements. Effort Estimation: Estimate the overall effort required for feature development, providing valuable input to project planning and scheduling. Cross-Functional Collaboration: Collaborate with verification, physical design, test generation, and mill code teams to develop features, fostering cross-functional teamwork and synergy. Pre-Silicon Design Sign-off: Sign off on design during the pre-silicon phase, ensuring readiness for tape-out and fabrication. Post-Silicon Validation: Validate hardware functionality post-silicon, conducting thorough testing to ensure feature integrity and performance. Required Technical and Professional Expertise Microarchitecture and Logic Design: 7 to 12 years of experience in microarchitecture and logic design, demonstrating proficiency in designing complex digital systems. VLSI Design in VHDL/Verilog: Experience with VLSI design using hardware description languages such as VHDL or Verilog, enabling efficient implementation of digital logic. Processor Architecture Understanding: Good understanding of processor architectures, including RISC and CISC, facilitating the development of features tailored to specific processor requirements. Designer Simulations: Experience in developing and performing designer simulations, ensuring functionality and performance goals are met prior to silicon realization. Design Closure and Verification Coverage: Proven ability to drive design closure, including test plan reviews and verification coverage analysis, ensuring comprehensive validation of designs. Preferred Technical and Professional Experience Power-Efficient Logic Design: Experience in designing power-efficient logic, optimizing designs for low power consumption without sacrificing performance. Physical Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical implementation and timing closure processes. Python Scripting: Proficiency in Python scripting, enabling automation of design tasks and enhancing productivity in design workflows. Preferred Education Master's Degree Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270511 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum (must haves) Bachelor's degree in electrical engineering or computer engineering with 3 to 9 years of experience or a master's degree in electrical engineering or computer engineering. 6+ years of experience in 5 or more of the following: Test Bench bring-up at SoC and strong programming skills in System Verilog, OVM and UVM. Test Plan development experience. Enabling regressions, maintaining QoV (quality of validation) with good functional/code/other coverage metrics. Familiarity with both simulation and emulation environments. Strong CPU/GPU architecture understanding. RTL Debugging module level or soc level system simulation failures. Building emulation models, enabling content Working with Validation Engineers and central CAD teams to support and maintain verification requirements in terms of Automation and tool flow support. Coordinating with Val team on CAD Requirement with support CAD, IT and Engineering Compute Teams. Act as focal point between design and tool vendors for issues and feature enhancements. Training/Supporting Validation Engineers in CAD tool flow and Infrastructure Monitoring and improve existing simulation environments and simulation efficiency. Experience with Performance Validation of GPUs and automation framework using Python is desirable Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 17 Days Ago job requisition idJR0274344 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications.Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to micro-architecture specifications.Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.Replicates, root causes, and debugs issues in the pre-silicon environment.Finds and implements corrective measures to resolve failing tests.Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.Maintains and improves existing functional verification infrastructure and methodology.Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum Qualifications:BS with 10+ years/MS with 8+ years industry experiencesExperience on Pre-Si validation on Emulation, preferably Zebu.Experience on validation at MCP.Experience with pre-Si verification with System Verilog OVM/UVM on content development Scripting languages such as Python, Simics.Good understanding of RTL, Verilog, VHDL.Preferred Qualifications:Experience with Synopsys simulation and coverage tools.Assertion based verificationRequirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 9 Days Ago job requisition idJR0274850 Job Details: About The Role : We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for one or more of the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. Qualifications: The ideal candidate will exhibit the following traits/skills: Excellent written and verbal communication skills Demonstrate Leadership ability in driving execution Demonstrate teamwork, problem solving and influencing skills Ability to work with different geographical locations Minimum Qualifications: Bachelors in Electrical/Computer Engineering or related field with 9+ years of experience. Or a Masters in the same fields with 7+ Years of academic or industry experience. Your experience should be in following At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.) SoC or IP DFT design, integration or verification EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools. Preferred Qualifications: Silicon enabling debug or test pattern development experience Design automation skills and proficiency in programming or scripting languages Structural design flows, including timing, routing, placement or clocking analysis High volume manufacturing requirements and test flows 3D, media and display graphics pipelines SoC architecture Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0272648 Job Details: About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 10+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience The years of experience mentioned above must focus on formal verification Preferred Qualifications: Knowledge of GPU Formal verification experience in at least one of these areasArbitration logic, low power design, memory controller, transaction router/bridge. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

locationsIndia, Bangalore time typeFull time posted onPosted 30+ Days Ago job requisition idJR0270512 Job Details: About The Role : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 5+ years of industry experience, or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 3+ years of industry experience Years of experience must include at least three of the following skills: Hardware architectures, system level IC design implementation knowledge of how to create end use scenarios IP level or SoC level validation experience Processor-based SoC level verification, in native Verilog, SystemVerilog and UVM mixed environments Verification tools such as VCS, waveform analyzer and/or third-party VIP/BFM integration (e.g. Synopsys VIPs) UVM verification Strong understanding of design concepts and ASIC flow Preferred Qualifications and experience that will make you stand out: Prior work on GDDR memory, power management, peripherals, datapath verification or PCIe Protocol is desirable Understanding of AXI-AMBA. Protocol variants is desirable Strong technical background in FPGA prototype emulation and debug Proven technical background in silicon validation, failure analysis and debug Validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART Prior hands-on automation script development and optimization using C/C++, Python Good understanding of embedded firmware/software development process Functional knowledge and experience in JTAG Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Looking for below - Architect/Lead ASIC designer/Lead Design verification/Lead Formal Verification/Lead Emulation/Lead Synthesis Engineer/Lead Implementation Engineer/Lead DFT Engineer/Lead Share your updated CV at jatin@smrd.in

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. Are you seeking an opportunity to work on delivering silicon solutions that have a planet-scale impact? The Data Processing Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer. You will join our front-end silicon team and be responsible for delivering cutting-edge, high performance, low power, scalable and programmable DPU silicon. Responsibilities As a Senior Silicon Engineer in the Data Processing Unit team, you will be validating silicon to solve complex problems in a datacenter. You will interact with the architecture team to develop a programmable silicon implementation. This position is expected to be highly visible and impactful. The vast breadth of domains required to build our DPU silicon gives the perfect opportunity to experience different areas of expertise. The depth required to solve complex engineering problems utilizes your experience and provides you with the perfect platform to shine and grow to the next stage in your career. Detailed Responsibilities Develop SystemVerilog/UVM based testbench. Work with vendors and IP providers to integrate their IP into testbench Develop and maintain test plans, test cases, and test scripts Execute test plans and analyze results Work closely with architecture, design and verification teams to ensure successful tapeout Participate in design and verification reviews Participate in the development of verification strategies and plans Qualifications BS and/or MS in Electrical Engineering or equivalent degree 8+ years of Design Verification experience Experience in System Verilog/UVM based testbench environment. Self-motivated and able to work effectively both independently and in a team. #SCHIEINDIA #AHSI Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. Show more Show less

You will contribute as a skilled Packet Core Specialist expert responsible for one or more key functions like Fault, Configuration, Performance, and Security. You will work independently within global guidelines, solve complex problems, and contribute to process improvements. You will also mentor and advisor, take responsibility for high-risk procedures, and collaborate with internal and external stakeholders to ensure seamless delivery of MS services. You have: 9-12 years with a bachelors degree in Telecommunications, Network Engineering, Computer Science, or a related field. Proven experience in packet core network design and planning for mobile and broadband networks, including EPC and 5G Core technologies. Expertise in packet core network elements such as MME, SGW, PGW, UPF, PCRF, and their interworking in both 4G and 5G environments. Experience with network optimization, traffic modeling, and capacity planning tools. It would be nice if you also had: Good analytical and problem-solving skills, with the ability to diagnose and resolve complex network issues. Knowledge of cloud technologies and virtualization (e.g., NFV, SDN, cloud-native 5G) is a plus. Excellent communication skills and the ability to collaborate effectively with cross-functional teams. You will lead the design and planning of packet core network architectures, including EPC (Evolved Packet Core), 5G Core, and other related technologies, ensuring scalability, security, and performance. You will perform capacity planning for packet core elements (e.g., MME, SGW, PGW, UPF) and ensure efficient resource allocation and utilization. Optimize network design to accommodate traffic growth while meeting quality of service (QoS) requirements. You will Collaborate with the implementation and operations teams to integrate new packet core components and technologies into existing networks. Oversee the testing and validation of network configurations and integrations. You will utilize traffic modeling tools and simulations to forecast future demand on the packet core network and identify potential bottlenecks or performance issues. You will design and implement security measures for packet core networks, including encryption, firewalls, and access control mechanisms, to safeguard data and ensure compliance with industry standards and regulations. You will work with vendors to select appropriate hardware, software, and technologies for packet core network infrastructure. Manage vendor relationships and ensure that vendors meet performance and delivery expectations. You will monitor packet core network performance using network management and monitoring tools. Analyze performance data to troubleshoot issues and propose solutions to optimize the network.

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Lead Software Engineer Location: Noida Experience: 4-6 Years Job Description Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence’s Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product. Job Responsibilities The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications Extensive experience developing large, high-quality, object-oriented C++ based applications is required Extensive experience with debugging and tuning of C++ code is required Expertise in data structures and algorithms is required Experience and understanding of EDA timing concepts and time constraints (SDC) is highly desirable Experience developing multi-core applications on Linux is highly desirable Experience developing on Linux with gcc is desirable Hardware knowledge and background in RTL design and/or verification is highly desirable. Position Qualifications B.E. in EE/ECE/CS or Equivalent Good understanding of Digital Electronics. Prior knowledge of Verilog and STA tools required. We’re doing work that matters. Help us solve what others can’t. Show more Show less