Silicon Subsystems RTL Design Engineer

As a member of the team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - At least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. - Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). - Experience in micro-architecture and design of subsystems. Preferred qualifications: - Experience in SoC designs and integration flows. - Proficiency in scripting languages such as Python or Perl. - Knowledge of high performance and low power design techniques. - Understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.,