4 Timingpower Analysis Jobs

As an experienced professional in ASIC development with a background in Electrical Engineering, Computer Engineering, or related fields, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your primary responsibility will be to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Working within a dynamic team environment, you will contribute to the innovation behind products loved by millions worldwide, focusing on verifying complex digital designs with a specific emphasis on TPU architecture and its integration within AI/ML-driven systems. Your role will also involve collaborating with cross-functional teams to design ASICs that enhance traffic efficiency in data centers. By leveraging your expertise in micro-architecture and logic solutions, you will be responsible for specifying and delivering quality designs for next-generation data center accelerators. Additionally, you will lead a team of Engineers in the design organization to deliver IPs or Subsystems, drive feature closure, and develop microarchitecture specifications in alignment with Architecture, Firmware, and Software teams. The ML, Systems, & Cloud AI (MSCA) organization at Google focuses on designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. As a member of this team, you will be at the forefront of driving innovation and shaping the future of hyperscale computing. Your contributions will prioritize security, efficiency, and reliability across all projects, from developing the latest TPUs to managing a global network. Your key responsibilities will include leading a team of Engineers, owning microarchitecture and implementation of IPs and subsystems in the networking domain, collaborating with cross-functional teams, driving design methodology enhancements, and identifying opportunities for Power, Performance, and Area improvements within the domains you oversee.,

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low power design techniques is preferred, along with an understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job: As a member of our team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. The ML, Systems, & Cloud AI (MSCA) organization at Google is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team works towards shaping the future of hyperscale computing, impacting users worldwide. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned.,

You will need a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, you should have at least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. It is also essential to have experience in the design and development of Security or Audio blocks, as well as with a scripting language like Perl or Python. Familiarity with DSI2 or MIPI C/D Phy is necessary. Ideally, you should have a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Preferred qualifications include experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture is also beneficial. As a part of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services. By researching, designing, and developing new technologies, the team aims to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Your responsibilities will include collaborating with architects to develop microarchitecture, performing Verilog/SystemVerilog RTL coding, functional/performance simulation debugging, and conducting Lint/CDC/FV/UPF checks. You will also participate in test planning and coverage analysis, develop RTL implementations meeting power, performance, and area goals, and be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up. Additionally, you will create tools/scripts to automate tasks, track progress, and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains.,