RTL Design Engineer, Core-IP, Silicon

You will need a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, you should have at least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. It is also essential to have experience in the design and development of Security or Audio blocks, as well as with a scripting language like Perl or Python. Familiarity with DSI2 or MIPI C/D Phy is necessary. Ideally, you should have a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Preferred qualifications include experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture is also beneficial. As a part of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services. By researching, designing, and developing new technologies, the team aims to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Your responsibilities will include collaborating with architects to develop microarchitecture, performing Verilog/SystemVerilog RTL coding, functional/performance simulation debugging, and conducting Lint/CDC/FV/UPF checks. You will also participate in test planning and coverage analysis, develop RTL implementations meeting power, performance, and area goals, and be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up. Additionally, you will create tools/scripts to automate tasks, track progress, and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains.,