At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms. The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms. We’re looking for a candidate who has the following skillsets: Extensive knowledge of Perl and Python Knowledge of dependency-checking via make, SCons LSF or other batch-queuing system (e.g. Grid, PBS, Open Lava), and script integration Using REST API (e.g. Jenkins, Jira) from Perl, Python Migrating scripts, script-libraries to different Linux OS releases Knowledge of SQL, relational database engines like MariaDB or PSQL, and integration with Perl/Python Knowledge of web technologies: Basic Apache setup, PHP, Javascript/Jquery, RSS automation These Skillsets And Knowledge Would Also Be Desirable BS/MS - Electrical / Computer Engineering. At least 7 years of of relevant experience. Updating/debugging TCL code embedded in a variety of tools, such as simulator, waveform-viewer, formal verification, in-house interpreter, etc. Knowledge of Verilog, SystemVerilog testbenches; some familiarity with methodologies like OVM or UVM; incorporate DPI or PLI models Some IT knowledge: NFS, memory/CPU profiling, NIS/DNS/LDAP, SMTP, syslog, cron, etc Jenkins install/configuration/management Module-files and modulecmd to manage tools and tool-versions Cloud deployment/maintenance: Amazon Web Services, MS Azure, IBM Cloud Experience with revision control like git or GitHub The position is based in Austin/San Jose/Bangalore (India) We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary Drives development of products and technologies and has material responsibility for the success of that product/technology. VIP PE is expected to be an expert in UCIe domain of Verification IP family- protocol and product-wise. PE main role is to help accelerate VIP portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a UCIe VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customer, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. PE is expected to work independently and collaborate with other team members ( RnD, Marketing, support) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel on average. Experience and Technical Skills required (edit as per the requirement): At least 5 to 8 years of experience with Verification and Design Working knowledge with UCIe domain and functional verification. Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Excellent problem-solving and debugging skills Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics/Computer Science or equivalent Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Description Design verification of ASICs for Palladium. Position is based in Bangalore. Will have to work at IP, Sub-System and SOC level verification. Test plan creation, functional coverage plan and coding of functional coverage bins. Will be involved in post silicon validation/bring up. Job Requirements Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology. Experience in functional coverage/code coverage/assertions development and closure. Experience in test plan creation. Exposure to PCIe and LPDDR verification. Strong debug skills Should be process oriented and have a passion for scripting/automation. Should be a good team player. Effective cross-team communication and documentation skill is strongly preferred. Minimal qualification requires BS/MS degree ECE or CS with 6+ years of experience in related fields. Behavioral Skills Required Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Ability to establish a close working relationship with both customer peers and management. Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect Define the sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc.) Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff. Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug Help develop and/or evaluate design and verification methodologies and participate in improving existing ones Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning Provide mentorship to the more junior team member What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12 -20 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-18 years of experience. Experience in creating architectural, micro-architectural, and register specifications. Verilog/System Verilog RTL coding with System Verilog assertions Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up) Expertise in high speed protocols (Ethernet). Should have worked on Full Chip Integration of Complex SoC design. Has worked on complex chips such as network processors, CPUs ,GPUs ,NOCs ,Switches , Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators Experience with scripting in Perl/Python/Shell Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. 4+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs and leading projects from concept to verification closure. Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage. We’re doing work that matters. Help us solve what others can’t. Show more Show less

L&T Technologies is looking to hire for SOC DV Lead role. Job Location : Bangalore Job Title : SoC DV Lead YEARS OF EXPERIENCE : 8+ Years JOB DESCRIPTION: Expertise in verifying SOC based on ARM and RISC CPU’s. Define and implement ASIC / SoC verification plans, and build verification test benches to enable ASIC, sub-system, SoC level verification. Develop functional tests based on a verification test plan. 8 to 12+ Years of experience in DV 3 to 6+ years of experience in AMS Verification is a must Experience in Co simulation (RTL + Spice) Good understanding on Analog blocks Experience in System Verilog, UVM is must Experience in WREAL, RNM, Vams modelling is a plus Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Responsibilities Protium is leading product in FPGA Emulation/Prototyping domain. This role is to provide essential Software/Hardware test environment to validate this system Technical Skills Required Bachelors / Masters in Electronic Engineering Proficient in Verilog / System Verilog Experience of FPGA platform The annual salary range for California is $108,500 to $201,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India. Summary The successful candidate will join a team designing and developing Lattice FPGA software tools. The candidate will contribute to delivering software solution for Lattice FPGA development with emphasis on Lattice synthesis tool. The candidate is expected to be an expert in FPGA synthesis core engine with knowledge on how to achieve optimal solution for a given architecture and be able to support next generation FPGA with best result in Fmax, Area, Runtime as well as memory utilization The candidate will team up with other synthesis developers and develop synthesis engine for various FPGA products. The responsibility also includes customer support, new software feature support as well as QoR improvement. The candidate is expected to maintain existing software products and interact with other teams to facilitate a value-added solution too. Accountabilities Develop logic synthesis tool for Lattice FPGA products. Synthesize logic designs from Verilog/VHDL RTL to structural netlist. Improve synthesis engine QoR. Create test designs with test benches to verify implementation and ensure high quality. Qualifications BS/MS/PhD in Electrical Engineering or Computer Science or Computer Engineering. Proficient with C/C++, Verilog/VHDL, logic design, Tcl and shell scripts. Strong background and experience in data structures and algorithms. Experience of logic design and EDA software is a must. Experience of logic optimization and technology mapping development is required. Experience of FPGA tool development is preferred. Strong written and verbal communication skills, and collaboration skill. Experience of multi-processing development is a plus. Solid understanding in FPGA architectures is a plus. 10+ years of experience in logic synthesis development in FPGA or ASIC domains Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches. Must be able to obtain and maintain a Department of Defense classified clearance Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT) Should possess intimate knowledge of DFT insertion flows Basic scan chain insertion using synthesis or other software tools Experience in compression scan insertion, LBIST and other scan technologies Intimate knowledge of memory build-in self-test (MBIST) Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals Debug and Analysis of failures to improve fault coverage Verification of ATPG testbenches and debugging root cause of simulation mis-compares Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687 Knowledge of timing analysis and equivalency checks would be added bonus Ability to work in collaborative team environment Prior experience with Cadence tools and flows is highly desirable Should be able to finish DFT tasks independently Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Self-driven and committed individual who can work in a fast-paced project environment We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Sr Principal Design Engineer Location: Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers. The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions. The role will require customer interactions including pre and post-sales activities, DV methodology review and customer support. Job Responsibilities Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics. Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment. Represent DV and technically work/lead team interactions with RTL, Subsystem and Performance for design verification tasks. Contribute towards defining, developing, and deploying new functional verification methodologies. Participate in interactions with Marketing, AE and Release team when required. Review project signoff and quality of DDR controller feature verification. Experience And Technical Skills Required At least 11+ years of relevant experience including design verification experience. Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Strong expertise in Verilog, SV with UVM methodology. AXI and/or CHI experience is highly desirable. Prior experience in leading and managing teams with expertise in any of DDR, PCIe, UCIe or USB is strongly required. Memory controller verification experience is a plus. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description RTL Design Engineer for DDR Memory Controller IP development team. The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4. The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines. Position Requirements BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. RTL Design using Verilog is a must. System Verilog experience and experience with UVM based environment usage / debugging is required. AXI3/4 experience is desired. DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must. Prior experience in IP development teams would be an added advantage. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Engineer Location: Ahmedabad Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary Drives development of products and technologies and has material responsibility for the success of that product/technology. MM VIP PE is expected to become an expert in the Memory domain of Verification IP family – protocol and product-wise. The memory domain has many protocols such as SDRAM protocols (DDR5), SGRAM protocols (GDDR6), Memory Controller and PHY protocols (DFI), and others. The Cadence VIP Portfolio includes Memory Models that enable advanced verification of these protocols. The PE’s main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre-sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a MM VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customers, providing training and developing collaterals. The PE will also need to translate high-level requirements from customers into a technical spec and drive the product definition that fits the customer needs. The PE is expected to work independently and collaborate with other team members (R&D, Marketing, Customer Support, Field Teams) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel and cross-site collaboration over multiple geographies (Asia Pacific, Europe, US-East, US-South and US-West). Job Responsibilities Leads projects with high resource, risk and/or complexity Develops and leads large and multiple cross-functional and cross-organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity Continually evaluates technology effectiveness/data interoperability of complex systems Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view. Experience And Technical Skills Required At least 4 – 8 years of experience with Design and Verification Experience with Developing Verification environments using System Verilog Working knowledge and experience with the UVM methodology Good experience on solving complex problems where analysis of situations or data requires an in-depth evaluation of various factors. Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results. Excellent problem-solving and debugging skills Familiarity with Memory protocols is a must. Knowledge of the DFI protocol is a plus. Qualifications BTech/BE/MTech/ME or equivalent with Electrical, Electronics & Comm or Computer Science Engineering Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities Implementation of DFT features into RTL using verilog. Understanding of DFT Architectures and micro-architectures. ATPG and test coverage analysis using industry standard tools. JTAG, Scan Compression, and ASST implementation. Gate level simulation using Synopsys VCS and Verdi. Support silicon bring-up and debug. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows Experience & Qualifications BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques. DFx experience implementing in finFET technologies. Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Experience with Fault Campaigns a plus. Strong problem solving and debug skills across various levels of design hierarchies. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded. Show more Show less

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do : Responsible for PDK evaluation, setup, customization, and flows definition Drive and implement specific Custom Design Automation flows such as Schematic entry, Layout design - color aware and DPT/MPT Parasitic Extraction for transistor level flow Device Modeling and Simulation environment in Synopsys' Custom Compiler PrimeSim XA circuit simulators Knowledge and hands-on experience in physical verification – DRC, LVS, and DFM checks Knowledge of Electrical verification like EMIR, ERC, PERC Knowledge of Analog cell characterization Knowledge of Reliability Verification Drive Interfacing between Digital and Analog/Mixed signal methodologies. . Develop Custom flows automation, rule deck customizations, improve productivity and efficiency. Train, Deployment and support of Automation flows to Design teams Debug flow issues and testcases from Design teams for Simulation, LVS, DRC, EMIR, post layout simulation. Assist Tape outs, final chip finishing runs, interface across foundry/customer for rulesets You will be reporting to Manager IP Modelling Team. What You'll Need: Must have a minimum Bachelor's degree in Electronic Engineering or a related program Must have 2 to 5 years of work experience in a CAD Automation engineer role. Experience with different Technology nodes (7nm, 5nm, 4nm, 3nm, etc) Experience with the different foundries (TSMC, SAMSUNG, etc) and design techniques. Good to have: Good knowledge of Analog/Mixed-signal Design and Development in Synopsys/Cadence Design environment. Good knowledge of EDA Tools and Methodologies in Analog/Mixed Signal Design and Development. Experience with standards and formats like Spice, CDL, LEF, DEF, Verilog, SPEF, GDS, OA, LIB, etc. Good knowledge of scripting skills – TCL, Python, C-Shell scripts, PERL, etc. Good knowledge of Data management aspects using Git/ SVN/ICManage / Cliosoft / Perforce / Methodics / etc. Good knowledge of 14nm/10nm/7nm/5nm/4nm/3nm finfet technologies Good knowledge of Deep Submicron Issues/technologies ( Understanding of Job submission and monitoring is a plus Understanding of tool License features and license administration is a plus ''We have a flexible work environment to support and help employees thrive in personal and professional capacities” As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

Description Amazon Devices is an inventive research and development company that designs and develops high-profile devices like the Kindle family of products, Fire Tablets, Alexa, Fire TV, Health Wellness, Amazon Echo & Astro products. This is an exciting opportunity to join Amazon in developing its next generation SOC’s for the machine learning enabled consumer products. We are looking for exceptional engineers and engineering leaders to join our SOC development team and help develop the next generation of chips based on a revolutionary architecture. The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers. Work hard. Have Fun. Make history. Key job responsibilities In this role, you work in a team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design. Work with Chip Architects to understand architecture and high-level product requirements. Convert Chip Spec into RTL using internal IPs and external IPs. Review Architecture and Design of custom IPs for integration into SOC’s. Design & Develop RTL for Interfaces, Power Management, Clocking, Reset, Test & Debug. Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management. Provide technical leadership through lead by example, mentorship and strong team work. Basic Qualifications BS degree or higher in EE or CE or CS 5+ years or more of practical semiconductor design experience including full-chip and subsystem RTL integration. Experience in micro-architecture definition from architecture guideline and model analysis. Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams. Experience with DFT tools for scan and BIST insertion Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams. Preferred Qualifications MS or PhD degree in Computer Engineering/Electrical Engineering or related field. Design experience in Datapath, flow control, Arbitration, FIFO, DMA , IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM’s AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C,UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;.) Other IP integration such as ADC, PLL, DLL, PVT sensors, GPIO & Debug (Coresight). In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators. SOC bring-up and post silicon validation experience Experience with early RTL power analysis. Experience with gate level testing and multi clock design practices. Successful tape outs of complex, high-volume SoCs in advanced design nodes Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. Company - ADCI - BLR 14 SEZ Job ID: A2914332 Show more Show less

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities: We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT Show more Show less

Job Description Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. Additional job functions include analyzing equipment to establish operating data and conducting experimental tests and evaluating results to confirm the device meets all requirements in the specifications. You may also run software simulations, selecting components and equipment based on analysis of specifications and reliability. As a Design Verification Engineer you may also review vendor capability to support product development. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry. About ASM Auto ASM (Application specific Microcontroller) business powers automotive and industrial MCU across multiple applications. ASM is now working on next generation Automotive MCU platform for all kind of vehicle applications e.g. Traction motor control, Charging, Lighting and Heating control, IC Engine management etc. This platform will churn out multiple differentiated products for Zonal networking in Software defined Vehicles (SDV) and superior real time control for EV Cars. Great opportunity to be part of this grounds up platform development across process nodes, IPs and SoCs. https://www.ti.com/applications/automotive/overview.html Responsibilities Complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs Active collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Final SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines Qualifications Qualifications: 2-5 years of DV experience in SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Skills Experience in one or many of the following: C based SOC DV, scripting (Python/Perl/Shell) knowledge, DV flow ownership for functional/Formal verification, UVM/System Verilog deep understanding, AMS/GLS/PAGLS/CPF/UPF based verification, Post silicon verification etc. Strong in digital design fundamentals, computer organization & architectures and bus protocols Excellent debugging skills with Verilog/VHDL designs Thorough knowledge in one or many of the standard protocols. Ex: AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray etc Work experience on C based environment with ARM/DSP multi-processor-based systems including the power aware simulations is a big plus Good problem-solving skills Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Exposure to CDC DV, Post silicon verification and functional safety is an added advantage Effective communication skills to interact seamlessly with all stakeholders Must be highly focused and remain committed to obtaining closure on project goals About Us Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

Job Location : HYderabad Experince Level 4+ years The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable). Show more Show less

We are currently seeking Verification Engineer with strong verification fundamentals to work in Switch Silicon group. Youll join a group of hardworking engineers to craft and implement the next generation innovative Switch Silicon chips. In this position, youll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest throughput and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace. What youll be doing: Verify Switch designs architecture and micro-architecture using advanced methodologies. Build reference models, verify and simulate chip blocks/entities according to specifications. Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW. You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure, test plans and tests and verify the correctness of the design at SOC level. Use sophisticated verification methodologies like e-specman, SV-UVM etc. What we need to see: BS (or equivalent experience) / MS with 4+ years of experience in design verification. Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.). Perl/python scripting language experience desirable. Ways to stand out from the crowd: Prior experience of Ethernet or InfiniBand Switches, and/or smartNICs or DPUs, and/or high-speed interconnects. Strong debugging, problem-solving and analytical skills. Scripting knowledge (Python/Perl/shell). Good social skills and ability desire to work as an excellent teammate. Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Sr Engineer, Digital Design Job Description Design key digital blocks such as clocks, reset paths, memory controller, NVMs etc. in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug Trace, TZC) and their integration requirements Design for Test skills on SCAN, MBIST boundary scan, JTAG and ARM DAP interface and general functional DFT understanding. Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces peripherals ATPG vectors, MBIST and BSCAN post silicon debug support. Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc. Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Sanas is revolutionizing the way we communicate with the world s first real-time algorithm, designed to modulate accents, eliminate background noises, and magnify speech clarity. Pioneered by seasoned startup founders with a proven track record of creating and steering multiple unicorn companies, our groundbreaking GDP-shifting technology sets a gold standard. Sanas is a 200-strong team, established in 2020. In this short span, we ve successfully secured over $100 million in funding. Our innovation have been supported by the industry s leading investors, including Insight Partners, Google Ventures, Quadrille Capital, General Catalyst, Quiet Capital, and other influential investors. Our reputation is further solidified by collaborations with numerous Fortune 100 companies. With Sanas, you re not just adopting a product; you re investing in the future of communication. We are seeking a highly skilled and experienced Staff Software Engineer with a passion for embedded systems development to join our innovative engineering team. In this role, you will be instrumental in designing, developing, and implementing software for our embedded platforms, potentially including Linux-based systems, small handheld devices, and more. Your expertise in areas like kernel development, device drivers, audio drivers, and single-board computers will be invaluable in shaping the future of our products. Key Responsibilities: Design, develop, and debug software for embedded Linux-based systems. Develop and maintain device drivers for various hardware peripherals on Linux. Investigate and implement solutions related to native audio drivers on Linux or Windows platforms. Develop software applications and system-level code for platforms similar to Raspberry Pi. Design and implement efficient and robust software for small, resource-constrained handheld devices. Participate in the full software development lifecycle, including requirements analysis, design, implementation, testing, and deployment Collaborate closely with hardware engineers to integrate software with embedded hardware. Optimize software for performance, power consumption, and memory footprint on embedded targets. Participate in code reviews and contribute to the improvement of our software development processes. Troubleshoot and resolve complex software issues on embedded systems. Contribute to technical documentation for software designs and implementations. Mentor and guide junior engineers on embedded systems development best practices. Stay up-to-date with the latest advancements in embedded systems technologies and trends. Must have qualifications: Proven experience (8-12 years overall software development experience) with a significant focus on embedded systems programming. Strong experience with Linux kernel development, including kernel configuration, module development, and debugging. Experience in developing device drivers for Linux (e.g., character drivers, network drivers, USB drivers). Hands-on experience working with native audio subsystems on Linux (e.g., ALSA) or Windows. Experience developing software for single-board computers like Raspberry Pi, BeagleBone, or similar platform Experience in developing software for small, battery-powered handheld devices with resource constraints. Strong proficiency in programming languages such as C and C++ Experience with embedded development tools and environments (e.g., cross-compilers, debuggers, emulators). Familiarity with communication protocols commonly used in embedded systems (e.g., I2C, SPI, UART, USB). Understanding of real-time operating systems (RTOS) concepts is a plus. Experience with build systems like Yocto Project or Buildroot is a plus. Familiarity with power management techniques in embedded systems. Experience with testing and validation methodologies for embedded software. Strong problem-solving and analytical skills. Excellent communication and teamwork abilities. Preferred qualifications: Experience with specific processor architectures (e.g., ARM, x86) used in embedded systems. Contributions to open-source embedded projects. Experience with security considerations in embedded systems development. Familiarity with hardware description languages (HDLs) like Verilog or VHDL Joining us means contributing to the world s first real-time speech understanding platform revolutionizing Contact Centers and Enterprises alike. Our technology empowers agents, transforms customer experiences, and drives measurable growth. But this is just the beginning. Youll be part of a team exploring the vast potential of an increasingly sonic future

Meet the Team Join our dynamic front-end design team at Cisco Silicon One, where innovation meets innovative technology! As part of the heart of silicon development at Cisco, you'll engage in every facet of chip design, from architecture to validation, using the latest silicon technologies to create groundbreaking devices. Cisco Silicon One is the only unified silicon architecture that empowers customers to deploy top-tier silicon across diverse applications, from top-of-rack switches to expansive data centres. Be a part of shaping Cisco's progressive solutions by designing and testing advanced ASICs that integrate networking, compute, and storage into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of our systems, using the latest technology. We're seeking a dedicated ASIC engineer with a proven track record in high-performance products, ready to make a significant impact in the industry. Join us and push the boundaries of what's possible! Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelor’s Degree in EE, CE, or other related fields with 6+ years or Master’s Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus. #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us! Show more Show less

FPGA/DSP Engineer 3+ years Experience in the FPGA based H/W, VHDL,Verilog code development. Good analytical ,abstraction and communication skills. Knowledge on DSP techniques, matlab, radar system is desirable. M.E / M.Tech In ECE /EEE, with specialisation in Instrumentation and Control or equivalent. First Class (>60%) B.E / B.Tech in ECE/EEE, First Class (>70%)

Staff IP/RTL Design Engineer for TPU Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 5-10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 5-10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"