2321 Verilog Jobs - Page 32

NK Securities Research is a leading financial firm that leverages cutting-edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High-Frequency Trading across different asset classes. As an FPGA Developer at NK Securities Research, your primary responsibility will be to design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will be instrumental in reducing system latency and enhancing performance, directly influencing trading outcomes. You will be tasked with developing high-performance RTL designs using VHDL or Verilog for FPGA-based systems, optimizing hardware implementations for ultra-low latency and high throughput, and ensuring thorough functional and timing testing of RTL designs to meet specifications. Additionally, you will be responsible for debugging and resolving issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration with hardware and software teams to seamlessly integrate FPGA solutions with the Software Trading Stack will be a key aspect of your role. Maintaining clear and comprehensive documentation of designs, test cases, results, and benchmarks is essential to ensure effective communication and knowledge sharing within the team. Preferred qualifications for this role include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field from top IITs. Proficiency in VHDL or Verilog/SystemVerilog, hands-on experience with industry-standard tools like Xilinx Vivado, expertise in writing testbenches and conducting simulation-based verification, familiarity with static timing analysis, and proficiency in debugging tools such as SignalTap, ChipScope, or ModelSim are desired. Exposure to high-speed interfaces like PCIe, Ethernet, or DDR, as well as a basic understanding of low-latency design principles and architecture, are considered advantageous. Candidates with a proven track record in delivering high-quality RTL designs, strong analytical and problem-solving skills, and the ability to work independently while collaborating effectively in a team environment are encouraged to apply. In return, NK Securities Research offers a competitive salary package, the opportunity to work in a dynamic and collaborative environment, career growth and development opportunities, catered breakfast and lunch, an annual international trip, and monthly team dinners.,

SoC Verification Engineer SoC Verification Engineer >> SoC Verification Engineer Post SoC Verification Engineer Required Experience 1 to 3 years Location: Bangalore,Delhi NCR,Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Must haves: Worked on IP level verification environment 1 to 3 years of experience Good experience with Verilog, System Verilog and UVM Experience with verification for protocols like AXI or AHB Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB Excellent Team Player Good To Have Experience of SOC Verification Experience of Formal verification Experience on verification of automotive protocols Email your resume to careers@truechip.net and mention position/location in the subject,

Company Overview Connectpro operates in the human-resources industry, specializing in recruitment and talent acquisition. Role And Responsibilities As a senior analog design engineer at Connectpro, you will be responsible for taking a subsystem of analog design through all phases of the design process. This includes: Creating the architecture of the analog subsystem Providing technical leadership to the team during execution Designing, simulating, and supervising the layout and verification processes Evaluating and debugging silicon samples You will be working with the latest Cadence analogue design tools including Virtuoso Composer, Verilog, HSPICE, and other PC-based tools like Matlab. The circuits you will be working on involve mixed signal blocks such as switched capacitor amplifiers, PLL, RAM, high-speed interfaces, references, IO circuits, data converters, and digital building blocks. Your role will also involve ensuring timely execution and collaborating with cross-functional teams like PE/TE. Experience with custom layout and analog verification is a plus. Candidate Qualifications To be successful in this role, you should possess the following qualifications: Bachelor's degree with 5-8 years of experience in CMOS, analog/power/mixed-mode IC design using tools similar to the ones mentioned above Strong fundamentals in CMOS analog design Excellent communication skills Ability to interact effectively with cross-functional teams Understanding of the semiconductor development flow Skills: hspice,semiconductor development flow,adc,,pll,icdesign,data converters,analog,layout/verification,dac,mixed signal,team management,cadence analogue design tools,custom layout,analog/power/mixed-mode ic design,simulation,evaluation/debug,amplifiers and filters,matlab,interact with cross functional teams,switched capacitor amplifiers,pmic,cmos process,cmos,,ram,ams,virtuoso composer,architecting,design,dll,,digital building blocks,references,analog verification,cmos,io circuits,hispeed interfaces,communication skills,verilog,analog design,

Become a Pioneer in Computing - Join Vicharak! At Vicharak , we stand at the vanguard of a computing revolution. Similar to the trailblazers at Bell Labs in 1947 who witnessed the birth of the transistor, we're revolutionizing the future of semiconductors through innovative FPGA technology. Unlike traditional processors, our FPGAs enable programmable changes in inner circuitry, unlocking new dimensions in parallelism, speed, and computing. Our groundbreaking VAAMAN hardware system, combining FPGA and SBC, epitomizes our innovation, and we're searching for talented individuals who share our fervor for this field. We invite researchers, developers, designers, engineers, and architects to join us in crafting the next era of computing. What You'll Learn: Software languages: C/C++, Python, HDL languages like Verilog and System Verilog. Utilize diverse tools, including compilers such as GCC and X86s, alongside IDEs like Visual Studio and PlatformIO. Master FPGA tools like Vivado, Radiant, and Efinix FPGAs. Develop adaptable skills to tackle challenges effectively and gain insights spanning from keyboards to complex servers. What You'll Work On: Engage in our thrilling projects, delving into various facets of our Acceleration framework encompassing AI Acceleration, Software Acceleration, and optimizing peripherals. Gain hands-on experience in Verilog and System Verilog, mastering the fundamentals of these languages. Join Us at Vicharak - Shape the Future of Computing! If you possess an unwavering interest in this field and an insatiable thirst for knowledge, we want to hear from you! Come be part of Vicharak and be at the forefront of molding the future of computing through our groundbreaking FPGA technology. For more insights, visit our website: https://vicharak.in

As an ideal candidate for this role, you should possess 3-5 years of experience in emulation/prototyping utilizing Cadence tool flows such as Palladium and Protium. Your expertise should extend to having a working knowledge of System Verilog and Verilog language semantics, along with familiarity with compilation flows associated with these languages. A solid understanding of SOC architecture and the AXI protocol is essential for this position. Your ability to comprehend and work effectively with SOC architectures and AXI protocol will be crucial to your success in this role. Moreover, strong communication skills and the capacity for effective team collaboration are highly valued. Your ability to communicate effectively and collaborate efficiently with team members will contribute significantly to the overall success of the projects you will be involved in.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Dear Candidate, We are hiring for Top MNC!! Location: Pune Work Mode: Hybrid-General Shift Contract: 1 Year Required Skills As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary. If interested, please share your updated cv to arthie.m@orcapod.work

Minimum qualifications: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field, or equivalent practical experience. 5 years of experience with ML/AI frameworks and libraries (e.g., TensorFlow, PyTorch, scikit-learn). Experience with hardware description languages (e.g., Verilog, SystemVerilog, VHDL). Experience with applying ML/AI techniques. Preferred qualifications: Experience with ML/AI applications in hardware design, verification and Low Power (e.g., formal verification with ML, coverage closure with ML). Experience with verification methodologies (UVM, OVM). Experience in data preprocessing and feature engineering, hardware architecture and microarchitecture. Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Excellent programming skills in Python or C++. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Research, design, and implement ML/AI algorithms techniques for various verification tasks, including test case generation, coverage analysis, bug prediction, and performance optimization. Develop and maintain tools and scripts for data collection, pre-processing, model training, and evaluation. Analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends. Build and train ML models for various verification applications, such as anomaly detection, pattern recognition, and prediction. Evaluate model performance and iterate to improve accuracy and efficiency. Participate in verification planning and develop test plans that incorporate ML/AI-driven techniques. Execute verification tests and analyze results to identify bugs and coverage gaps. Develop and maintain verification tools and scripts to automate verification tasks.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in micro-architecture and design of subsystems. Preferred qualifications: Experience in SoC designs and integration flows. Experience with scripting languages (e.g., Python or Perl). Knowledge of high performance and low power design techniques. Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing ASICs used to accelerate and improve traffic in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and logic solutions, and evaluate design options with complexity, performance, power and area in mind. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Own microarchitecture and implementation of subsystems in the data center domain. Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Perform Quality check flows like Lint, CDC, RDC, VCLP. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive power, performance and area improvements for the domains owned.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience with one scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Prior internship or co-op experience in a hardware design or verification role within the semiconductor industry. Experience developing and maintaining verification testbenches, test cases, and test environments. Experience through coursework or academic projects involving simulation, testbench development, or formal verification techniques. Familiarity with industry-standard verification methodologies such as UVM (Universal Verification Methodology) or OVM (Open Verification Methodology), even if at a foundational level. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Provide test plans including verification strategy, environment, components, stimulus, checks and coverage, and ensure documentation is easy to use. Run pre-defined test cases and test benches, analyze simulation results, and identify discrepancies or failures. This includes debugging basic issues and collaborating with senior engineers to resolve more complex problems. Under guidance, contribute to the development of simple verification components such as monitors, checkers, or basic test sequences, and assist in maintaining existing verification infrastructure. Record test results, document bugs and their replication steps, and provide regular updates on verification progress to the team, highlighting any critical issues or roadblocks.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with performance, power, and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design and more to specify and deliver high quality designs for next generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Own implementation of IPs and subsystems. Work with Architecture and Design Leads to understand micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance, and Area improvements for the domains.

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Minimum qualifications: Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience. 5 years of experience with static timing analysis, synthesis, physical design & automation. Experience in physical design tool automation such as synthesis, P&R and sign-off tools. Preferred qualifications: Experience in extraction of design parameters, Quality of Results metrics, and analyzing data trends. Knowledge of timing constraints, convergence and signoff. Knowledge of parasitic extraction tools and flow. Knowledge of Register-Transfer Level (RTL) languages (e.g., Verilog/SystemVerilog). Knowledge of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR) and PDV signoff methodologies. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Drive the sign-off timing methodologies for mobile System on a chip (SoCs) to push Power Performance Area (PPA) and yield. Analyze power performance area trade-offs across different methodologies and technologies. Work on prototyping of subsystems to deliver optimized PPA recipes. Work with cross-functional architecture, Internet Protocols (IPs), design, power and sign-off methodology teams. Work with foundry to refine signoff methodology to improve convergence and yield.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qualifications: Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging. Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD. Experience with STA constraints development and analysis for DFT modes and SDF simulations. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL). About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation. Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port (TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns. Participate in post-silicon activity like bring up, diagnostics and characterization. Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with digital logic design, computer architecture, and circuit theory. Experience in scripting language (e.g., Python, Perl) or a hardware description language (e.g., Verilog, VHDL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience in low-power design verification. Experience developing and maintaining verification testbenches, test cases, and test environments. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design integration. Experience in Verilog or Systemverilog coding. Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features. Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior RTL Design Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our devices. In this role, you will be responsible for defining the micro-architecture and implementing the corresponding RTL for advanced functional blocks. You will participate in the design verification and bring-up of such blocks by writing relevant assertions, debugging code, test benches, test harnesses, and otherwise interacting with the extended team. You will participate in the lab bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data, proposing experiments, etc. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware Engineering, and Software Engineering, to architect and implement complex functional block that enable development of world-class hardware devices. In this role, you will: Design world class hardware and software Communicate and work with team members across multiple disciplines Develop detailed design specifications and documentation Perform RTL coding and synthesis Work with Partners/Supplier to optimize and customize their products Run industry standard code quality tools and fix issues found by them Participate in test plan and coverage reviews The ideal candidate should have experience with RTL development environments, fluency in modern hardware description languages. They should have developed complex IP blocks from scratch that have successfully been integrated in SOCs or other such silicon that have been productized in consumer devices. They should be familiar with modern SoC architectures, various interconnect topologies such as AMBA AXI, APB, AHB, and implementations. Experience with I/O interfaces such as SPI, I2C, I2S, PDM, and MIPI CSI/DSI/Slimbus/Soundwire is preferred. Experience with memory instantiation and memory compilers is also preferred. We are looking for a self-driven individual who can work with architects, HW and SW developers and can quickly resolve blocking issues. If you have the required skills and experience, we encourage you to apply for this exciting opportunity to join our growing hardware design team. Masters degree in Electrical/Computer Engineering or related field 7+ years of RTL development experience with a record of taping out production silicon Experience with design development using Verilog/SystemVerilog Experience in defining micro-architecture from architecture guideline and model analysis. Experience in performance/power/area analysis and trade-offs Proficient in design methodologies and EDA tools Experience working with Synthesis, timing closure, and design constraints Excellent problem-solving and debugging skills Ability to work collaboratively in a team environment and communicate technical ideas effectively PhD in Computer Science, Electrical Engineering, or related field Experience with design of video/graphics pipeline and image processing algorithms Familiarity with display panel and display driver IC technologies Experience with ARM and various DSP ISA Experience debugging system-level issues Experience in entire design flow from architecture to final silicon. Good programming skills in C/C++ and scripting skills in Python, Tcl, and/or Perl 10 years or more of practical experience Experience with wide variety of low power design techniques Working experience with high performance industry standard buses like AMBA AXI4 Experience in integrating third party IP blocks, building top level modules, defining clock domains and power domains Large breadth of knowledge from architecture through physical design Knowledge of FPGA and emulation platforms Knowledge of SoC architecture Excellent verbal and written communication skills

Job Title Firmware and Controls Designer Job Description You have the opportunity to be part of an exciting team and contribute to the design, development and maintenance of Magnetic Resonance Imaging (MRI) systems. In this role of Firmware and Controls Designer , you are responsible for the development and maintenance of MR Hardware Subsystems/Components and will gain substantial knowledge of complex systems in medical imaging environment. Together with a multidisciplinary team of engineers, you play a crucial role in getting these systems/sub-systems to the required performance, by owning the design, development, testing, and maintenance of embedded systems and safety/mission critical embedded software and firmware, that control various functions of MRI sub-systems. This requires broad orientation, conceptual skills and a can do mentality, keeping abreast with all trends and advancements in technology and medical imaging. You are a part of Hardware Engineering Group under MRI Business, located at Philips Healthcare Innovation Centre (HIC) Pune. HIC is playing a key role in Philips global strategy for Diagnostic Imaging. With Philips HIC, the foundation was laid to touch billions of lives and reiterate Philips commitment towards healthcare growth markets You are responsible for : Requirements, design, implementation, test and integration of module/sub-system in accordance with the higher-level architectural requirements and design specifications Ensuring that the design is consistent with the higher-level architecture and requirements Ensuring that the proposed design would have the safety, reliability and quality features built-in Responsible for ensuring that the design meets the performance, quality and cost criteria Conduct concept and feasibility studies. Leads the introduction of new technologies Ensuring that there is proper documentation per standards for the developed design Ensuring the mutual consistency and efficient integration of the separate components in modular design that meets the product specification Ensuring that his design modules meet the product certification requirements Drawing up personal schedule and reports on progress Defining and assessing the Work Breakdown Structure/planning/costs of his/her area Being abreast of technical developments in own field through study of literature and technical contacts Mentoring/guiding/hand-holding young engineers in the team and helping them ramp-up well Maintaining product and company reputation by complying with country specific regulations To succeed in this role, you should have the following skills and experience: Completed engineering studies at University level; BE/BTech/ME/M-Tech in Electronics or Electrical Engineering, with 8 to 12 years of experience Experience in complete life-cycle management of embedded software, preferably for medical products Expert in C, C++ and other embedded programming languages Proficient in hardware description languages like VHDL, Verilog etc. Knowledge of Software Design Life Cycle (SDLC) Good knowledge of modern OS coding techniques, IP protocols and hardware interfaces Experience in 16/32-bit microcontroller-based design and programmable devices (FPGA/CPLD/SoC etc.) and their interface Knowledge of communication interfaces like RS232, RS485, CAN, EtherCAT, Ethernet and USB Hands-on experience in developing control software for close-loop systems in a mechatronics environment Hands-on experience in using simulation and implementation tools such as MATLAB and SIMULINK Solid knowledge of digital signal processing and control theory Excellent debugging skills - ability to understand and debug problems across hardware/software boundaries Experiences in real-time operating systems Experience in printed circuit board bring up and testing Knowledge of software tests and static code analyses Knowledge of firmware development environments such as IAR or Eclipse as well as version control systems like GIT Should have experience in DFMEA and design of Fail-Safe Systems and Sub Systems Experience in design of a communication gateway will be an added advantage. Knowledge of IEC 60601 standards will be an added advantage Knowledge of Global Medical Quality and Regulatory Standards e.g. IEC, FDA, UL, CE, CSA etc. Hands-on experience with tools like Agile, Clear-quest, Windchill or equivalent Disciplined team worker, ability to work independently Result oriented team player Ability to present and articulate ideas to key stakeholders and leadership team Excellent communication skills and Positive can do attitude Quality mindset in design and documentation Global and Cross-functional Experience/Skills in a Matrix Organization will be an added advantage. If you re interested in this role and have many, but not all, of the experiences needed, we encourage you to apply. You may still be the right candidate for this or other opportunities at Philips. Learn more about our culture of impact with care here .

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing: You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies. Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Work on advanced verification methodologies like SV/UVM. Perform functional coverage driven verification closure. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B. Tech. / M. Tech. , or equivalent experience. 5+ years of relevant experience. Experience in verification of complex IPs/units and sub-systems. Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Expertise in Verilog. Knowledge in SystemVerilog or similar HVL / UVM or VMM. Ways to stand out from the crowd: Experience in memory subsystem or network interconnect IP verification. Debugging and analytical skills with sound scripting knowledge. Good communication and excellent team player. #LI-Hybrid

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What you ll be doing: Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What we need to see: BS / MS or equivalent experience. 5+ years of design experience. Experience in RTL design of complex design units for at least two or three projects. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways to stand out from the crowd: Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Leadership experience in leading small 2-3 member teams. Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. #LI-Hybrid

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of verification principles and coverage. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Responsibilities Lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. (20%) Ensure the definition and implementation of test and verification plans. (20%) Collaborate with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements.(10%) Monitor and analyse coverage reports to ensure thorough verification. (10%) Identify and resolve verification issues and bugs, ensuring timely project delivery. (10%) Continuously improve verification processes, methodologies, and tools. (10%) Manage project schedules, resources, and deliverables to meet deadlines. (10%) Oversee the writing and debugging of System Verilog assertion.(10%) Minimum Qualifications 8+ years of relevant experience in SOC verification. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design verification and team management. Proficiency in System Verilog and assertion-based verification. Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g., VCS, Questa Sim). Experience with SoC design verification. Knowledge of HVL methodology (UVM/OVM) with the most recent experience in UVM. Experience with formal verification. Experience taping out large SoC systems with embedded processor cores. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification. Excellent problem-solving skills and attention to detail. Desired Qualifications Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).