2321 Verilog Jobs - Page 36

Who We Are Optiver is a global market maker founded in Amsterdam, with offices in London, Chicago, Austin, New York, Sydney, Shanghai, Hong Kong, Singapore, Taipei and Mumbai. Established in 1986, today we are a leading liquidity provider, with close to 2,000 employees in offices around the world, united in our commitment to improve the market through competitive pricing, execution and risk management. By providing liquidity on multiple exchanges across the world in various financial instruments we participate in the safeguarding of healthy and efficient markets. We provide liquidity to financial markets using our own capital, at our own risk, trading a wide range of products: listed derivatives, cash equities, ETFs, bonds and foreign currencies. In Asia Pacific, Optiver was one of the first global market makers to establish a presence in the region, with the incorporation our Sydney office in 1996. Since then, we have expanded our footprint by establishing offices in Taipei (2005), Hong Kong (2007), Shanghai (2012) and Singapore (2021). The business in Mumbai is newly established and deemed to be an integral part of the APAC strategy, with an anticipation of significant growth over the coming years. What You'll Do We are looking for an FPGA Development Team Lead to hit the ground running as one of the founding members of our Mumbai FPGA & low latency development team, working on Optiver's execution platforms. You'll be focused on achieving best-in-market trade execution on the highly competitive Indian exchanges: NSE, BSE and MCX. But you won't be alone - you'll be backed by a strong collaboration with established FPGA & low latency development teams in Sydney and Shanghai plus gain exposure to the challenges in execution in Optiver's global businesses including in the USA and Europe. As a leader you will have a strong relationship with internal stakeholders including the trading, risk, compliance, and research teams who will all be collocated with you in the Mumbai office. You'll define the future of our execution platform and execute that vision with your mixed team of FPGA developers and low latency software developers, and through influencing teams in the rest of the Asia Pacific region. You will also be responsible for building that team and growing your developers to reach their potential. As this is a hybrid role, you'll still have the opportunity to be hands-on with some VHDL and C++. The developers in your team seek out business problems and design innovative solutions, owning their changes end-to-end including understanding the business problem, design, implementation, testing, deployment and monitoring. They are specialists in hybrid FPGA/software system design and consider which parts of the system are in the FPGA or in software. Our development is often fast paced, fulfilling and rewarding, with the ability to work on features and see them running in production within days. Other responsibilities include: Build and run a high performance mixed FPGA development & low latency software development team, including managing performance, career development and delivery. Define the architecture of our ultra low latency trading stack in collaboration with other senior developers. Contribute to the vision and strategy for Optiver's Asia Pacific execution capability. Implement and/or build solutions to enable our low latency trading and make Optiver number one status in Indian markets. Work with stakeholders across the business in a highly collaborative, flat structure. Own the automated trading risk of our ultra low latency trading system, defining standards and practices to manage return on risk. Who You Are We need our next FPGA Team Lead to be someone with: 5+ years experience in FPGA development in financial services/capital markets. Experience leading and developing a team. Experience working through the full development lifecycle with responsibilities including gathering requirements, development, testing, deployment, monitoring and ongoing maintenance. You will also have experience leading projects. Proficient in one or more of the following: VHDL, Verilog, SystemVerilog. Basic skills in C++ (or something comparable) and Python. An understanding of computer networks and protocols (TCP/IP/UDP). What You'll Get You’ll join a culture of collaboration and excellence, where you’ll be surrounded by curious thinkers and creative problem solvers. Driven by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, working collectively to tackle the toughest problems in the financial markets. In addition, you’ll receive: Competitive remuneration, including an attractive bonus structure that is unmatched in the industry. We combine our profits across desks, teams and offices into a global profit pool, fostering a truly collaborative environment. The opportunity to work alongside diverse, intelligent, and driven peers in a rewarding environment. Ownership over initiatives that directly solve business problems. Training, mentorship and personal development opportunities Competitive benefits A work-from-home allowance and support DIVERSITY AND INCLUSION Optiver is committed to diversity and inclusion. We encourage applications from candidates from any and all backgrounds, and we welcome requests for reasonable adjustments during the process to ensure that you can best demonstrate your abilities. Please let us know if you would like to request any reasonable adjustments by contacting the Recruitment team via careers@optiver.com.au.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced verification engineer with a passion for innovation and technology. You thrive in a dynamic environment and are eager to take on challenges in the field of IP verification. You have a solid understanding of HVL-based test environments and are proficient with one or more industry-standard simulators. Your expertise extends to verification methodologies such as UVM/VMM/OVM, and you are familiar with HDLs like Verilog and scripting languages such as Perl. You are a problem solver with excellent communication skills, capable of working independently and as part of a global team. You are excited to contribute to the DesignWare IP Verification R&D team at our Bangalore Design Center, India. What You’ll Be Doing: Implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores. Performing Verification tasks for IP cores, focusing on domains such as USB, PCI Express, Ethernet, and AMBA. Collaborating closely with the RTL design team and other expert Verification Engineers globally. Engaging in Test planning, Test environment coding at both unit and system levels, Test case coding, and debugging. Coding and analyzing functional coverage and meeting quality metric goals. Managing regression processes to ensure comprehensive verification. The Impact You Will Have: Enhancing the robustness and reliability of our IP cores, ensuring high-quality deliverables. Contributing to the development of innovative solutions that drive the Era of Smart Everything. Reducing the time-to-market for our customers by ensuring their products meet performance, power, and size requirements. Supporting the integration of more capabilities into SoCs, enabling differentiated products. Participating in a global team effort to advance cutting-edge technologies in chip design and software security. Ensuring the successful verification of complex IP cores, contributing to the overall success and reputation of Synopsys. What You’ll Need: BS/BE in Electrical Engineering with 5+ years of relevant experience or MS with 3+ years of relevant experience in IP core and/or SOC verification. Proficiency in developing HVL-based test environments and implementing test plans. Hands-on experience with industry-standard simulators such as VCS, NC, and MTI, and relevant debugging tools. Strong understanding of verification methodologies like UVM/VMM/OVM. Familiarity with Verilog and scripting languages such as Perl. Basic understanding of functional and code coverage. Excellent written and oral communication skills, along with strong analytical, debugging, and problem-solving abilities. Who You Are: A self-driven individual with a passion for technology and innovation. A collaborative team player with the ability to work effectively in a global team environment. A detail-oriented professional with a commitment to delivering high-quality work. A proactive learner who stays updated with the latest industry trends and technologies. The Team You’ll Be A Part Of: You will join the DesignWare IP Verification R&D team at our Bangalore Design Center, India. Our team is dedicated to developing and verifying the DesignWare family of synthesizable cores. We work on a variety of domains, including USB, PCI Express, Ethernet, and AMBA. Our collaborative and innovative environment supports continuous learning and growth, allowing you to make a significant impact on the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Role Overview We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Location: Bengaluru, Karnataka Experience: Minimum 3 Years of EdTech/IT/Corporate/Institutions Qualification: BE, BTECH, ME, MTECH, MCA (Any Degree) Shift Timing: 9:00 am to 6:00 pm (Mon to Fri) 9:00 am to 1:00 pm ( Sat) Skills & Requirements: Excellent communication skills written and verbal and negotiation skills. Fluent English speaking is mandatory. Strong Training experience highly preferred in VLSI, Verilog, HDL, VHDL/ Verification / Digital Electronics / Physical Electronics / Analog Electronics. Hands on programming with Verilog, Linux operating systems, Digital system design, SV, UVM, PGA. Knowledge of functioning of academic institutions and placement process . The candidate should have good interpersonal skills and networking in the market. Multi-tier architecture knowledge. Excellent self-management skills (task lists, status reports, prioritization). Commitment to quality and timely deliverable. Desire to understand the business. Roles & Responsibilities: Conduct technical training for graduates, professionals, and corporate employees. Develop customized training content, assessments, and course materials. Organize and deliver college and corporate workshops. Guide hands-on project work and mentor large student groups. Manage complete training lifecycle from analysis to evaluation. Ensure high-quality and effective training delivery. Lead and mentor trainers and developer teams. Coordinate with stakeholders to align training with business needs. Ensuring quality delivery to students. Provide timely feedback and performance evaluation to improve learner outcomes. Provide programming direction to a team of trainers. Job Type: Full-time Pay: ₹35,000.00 - ₹65,000.00 per month Schedule: Day shift Education: Bachelor's (Preferred) Experience: VLSI Trainer: 3 years (Preferred) Verilog: 3 years (Preferred) Edtech: 3 years (Preferred) Language: English (Preferred) Work Location: In person

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X). Staff Design Verification Engineer The Industrial Converter Technology group develops leading edge Signal Chain solutions for Industrial and other applications. The group is seeking a Staff Verification Engineer who must have a proven track record of verifying complex mixed/digital signals ICs. The team handles verification of the products which include digital signal processing data-paths, sensors, high speed interfaces, and sub-systems. Candidate will work with the latest verification methodologies on designs ranging from individual blocks to sub-system level verification. Job Responsibilities: Verification of sub-systems using leading edge verification methodologies. Experience with development of verification plan and verification environment from scratch on multiple projects. Verification of blocks using System Verilog and UVM. Should have worked on scoreboard assertions, functional coverage, formal verification etc. to reach verification goals Take complete ownership for a complex feature verification and mentor & guide junior verification engineers. Define and implement improvements in verification flow and methodology. Gate level simulations and debug at sub-system level. Job Requirements: Bachelor's or Master’s degree in Electronics Engineering with 8+ years of experience in digital verification. Expertise in Verilog, System Verilog, UVM, object-oriented programming, scripting and automation with Perl or Python. Firm understanding of constrained random functional verification, coverage, and assertions. Expertise in test plan development and development of verification environments from ground up. Extensive experience with verification of complex blocks, regressions and coverage closure. Experience with gate level simulations and debug. Excellent debugging, analytical and problem-solving skills. Strong inter-personal, teamwork and communication skills. Expected to be highly independent, proactive and result-oriented to achieve verification goals. Preferred qualifications: Knowledge of SPI, OTP/MTP, UART and I2S protocols.. Experience in technically mentoring, coaching junior engineers. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days

About this opportunity Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do - Design and implement FPGA-based Radio and RAN Compute solutions - Develop and optimize FPGA designs for performance, power, and cost-efficiency - Collaborate with hardware and software engineers to integrate FPGA solutions into larger systems - Apply industry-standard tools and methodologies for FPGA development and implementation - Research and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning - Document design specifications, test procedures, and results - Participate in design reviews and contribute innovative ideas to improve FPGA solutions You will bring To be successful in the role you must have: - 5+ years of experience in FPGA development - Comprehensive knowledge of: - FPGA technology, design environments, and design methodologies - FPGA design tools (e.g., Vivado, Quartus, or similar) - Hardware description languages (HDL), such as Verilog or VHDL - Experience with various communication protocols DDRX, AXI4, PCIE, SPI, I2C, embedded processing - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - Familiarity with hardware architecture and digital signal processing - Excellent problem-solving and analytical skills - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent Primary country and city: India (IN) || Bangalore Req ID: 768579

About this opportunity Are you passionate about driving innovation and working on groundbreaking 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new insights are championed, and you are encouraged to develop new skills? We are looking for an FPGA Designer to join the Ericsson Silicon organization. You will work with a group of dedicated engineers passionate about developing world-class Radio and RAN Compute products. You will play a key role in the FPGA team developing and integrating complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do - Design and implement FPGA-based Radio and RAN Compute solutions - Develop and optimize FPGA designs for performance, power, and cost-efficiency - Collaborate with hardware and software engineers to integrate FPGA solutions into larger systems - Apply industry-standard tools and methodologies for FPGA development and implementation - Research and stay updated on the latest advancements in FPGA technology, including academia and industry trends in AI and Machine Learning - Document design specifications, test procedures, and results - Participate in design reviews and contribute innovative ideas to improve FPGA solutions You will bring To be successful in the role you must have: - 5+ years of experience in FPGA development - Comprehensive knowledge of: - FPGA technology, design environments, and design methodologies - FPGA design tools (e.g., Vivado, Quartus, or similar) - Hardware description languages (HDL), such as Verilog or VHDL - Experience with various communication protocols DDRX, AXI4, PCIE, SPI, I2C, embedded processing - Experience with scripting languages such as Python, Tcl, shell scripting, etc. - Familiarity with hardware architecture and digital signal processing - Excellent problem-solving and analytical skills - Excellent English verbal and written communication skills - High self-motivation and the ability to work independently while being a great teammate - A track record of successful cross-team and cross-site cooperation - A Masters degree in Electrical or Computer Engineering or equivalent Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 768579

Job Title : SoC Architecture & RTL Engineer Company Overview Morphing Machines is a fabless semiconductor company focused on developing dynamic real-time reconfigurable RISC-V compliant dataflow accelerators. Our innovative technology aims to revolutionize hardware acceleration for high-performance computing and energy-efficient systems. Job Summary We are seeking a highly experienced SoC Architecture & RTL Engineer to design, implement, and optimize complex digital systems for next-generation computing platforms. This role offers the opportunity to work on cutting-edge SoC architectures involving high-speed interfaces and industry-standard protocols. Key Responsibilities Design and develop SoC architecture and RTL for complex digital systems. Work on CPU, GPU, and DSP pipelines, cache coherence protocols, and network-on-chip (NoC) designs. Integrate and validate PCIe, CXL, DDR, Ethernet, and other high-speed IPs. Ensure compliance with industry-standard protocols such as AXI, TileLink, PCIe, UCIe, and CXL. Perform simulation, synthesis, and optimization to meet performance and power targets. Collaborate with cross-functional teams for silicon delivery. Debug and resolve design and integration issues. Continuously explore and adopt new tools, methodologies, and technologies. Required Skills and Qualifications Bachelor s or Master s degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. 10+ years of experience in SoC architecture and RTL engineering. Strong expertise in digital design concepts, computer architecture, and hardware description languages (Chisel, Verilog, or VHDL). Hands-on experience with PCIe, CXL, DDR, Ethernet IPs. Experience with AXI, TileLink, PCIe, UCIe, and CXL protocols. Proficiency with digital design tools, simulation, and synthesis flows. Excellent problem-solving, communication, and teamwork skills. Ability to work independently in a fast-paced environment. Preferred Skills Experience in CPU/GPU/DSP core pipeline design and cache coherence protocols. Exposure to network-on-chip (NoC) architectures. Familiarity with power and performance optimization techniques. What We Offer Opportunity to work on innovative semiconductor technology. Collaborative, flexible, and inclusive work environment. Competitive compensation package. Exposure to cutting-edge hardware-software co-design challenges. Apply Now

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry s technology leadership. An opening exists for Technical Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you wont just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment youd like to participate in, wed like to hear from you! As a Technical Staff Design Engineer, your job will entail the following: Lead the Design planning of pad rings and package substrates, bump pattern construction. Dynamically define and optimize pad ring connectivity. Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,) Interface with and support Architect, PD, PE, technology development and foundries teams. Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds. Additional responsibilities include: Collaborate closely with the Manager to define team structure, skill requirements, and hiring strategy for the local IP development team. Support and participate in end-to-end recruitment activities, including job description creation, candidate screening, interviews, and onboarding. Help identify and engage top technical talent through various sourcing methods in alignment with project and business goals. Assist in establishing a strong, high-performance team culture by supporting team integration, training, and knowledge-sharing initiatives. Work cross-functionally with HR, Talent Acquisition, and Engineering leadership to ensure a streamlined hiring process and effective team ramp-up. Contribute to the development of a scalable team that aligns with long-term IP roadmap and organizational growth. Requirements/Qualifications: B.S or M.S degree in electrical engineering with 12+ years of related experience Prior experience in IC and multicore SoC designs Experience with front-end CAD tools (eg. top-level I/O planning tools) is required. Experience with Verilog/System Verilog is required Familiarity with Verilog models and Liberty files Experience in Fin-Fet technologies is a plus. Scripting experience or knowledge is a plus. Excellent analytical, communication (written and verbal), and documentation skills Excellent problem solving and debugging skills. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Job Title: Formal Verification Engineer Location: Bangalore Experience: 4+Years Job Type: Full-time Industry: Semiconductor / ASIC Design / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs. Key Responsibilities: Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, sequential equivalence checking , and formal coverage. Analyze formal results, identify unreachable or vacuous properties, and refine models. Collaborate closely with RTL designers, DV engineers, and architects. Integrate formal into overall verification methodology and sign-off. Document and present formal verification methodologies, assumptions, and results. Required Skills: 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin). Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification. Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog. Familiar with formal coverage metrics and convergence techniques. Experience in debugging complex design bugs using formal tools. Ability to abstract and model designs or protocols at different levels. Desirable Skills: Familiarity with safety-critical designs (ISO 26262, DO-254) is a plus. Knowledge of common protocols: AXI, AHB, PCIe, Ethernet, etc. Exposure to sequential equivalence checking and abstraction modeling. Understanding of simulation-based verification and integration with formal. Proficiency in scripting (Python, Perl, or TCL) for automation. Interested can Share CV to sharmila.b@acldigital.com

Job Title :IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging. Basic Job Deliverable:Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera SV/UVM Functional verification Expertise in Vivado for simulation debugs Qualification:B.E/M.E/M.Tech Interested can Share CV to sharmila.b@acldigital.com

Job Title: Functional Verification Engineer Location: Bangalore Experience: 4+ Years Job Type: Full-time Industry: Semiconductor / VLSI / ASIC Design Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/SoC verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery. Key Responsibilities: Develop and execute verification test plans based on design specifications and architecture. Design and implement testbenches using SystemVerilog and UVM methodology. Create constrained-random and directed test cases. Build verification components (agents, monitors, scoreboards, checkers). Perform coverage analysis (code and functional) and close coverage gaps. Debug simulation failures and work closely with design and architecture teams. Conduct regressions and analyze results for functional and performance issues. Document test plans, verification environments, and test results. Participate in design and verification reviews. Required Skills: 4+ years of hands-on experience in functional verification of IP/SoC. Strong knowledge and working experience with SystemVerilog and UVM . Familiarity with RTL design (Verilog/VHDL). Experience in coverage-driven verification, assertions, and functional coverage closure. Proficient in using simulators like VCS, Questa, or Incisive. Good scripting skills in Perl, Python, or Shell for automation. Strong debugging skills using simulation waveform viewers. Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc Interested can Share CV to sharmila.b@acldigital.com

Job Description Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required: Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints Additional Information Soft Skills and Cultural Fit Strong communication skills to articulate design concepts and collaborate with multi-disciplinary teams Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Hi, Greetings from ACL Digital, Looking for CPU Verification Engineers Exp level: 4+years Location: Banglore Job Description: We are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of high-performance, low-power CPU cores by developing scalable testbenches, driving complex test scenarios, and ensuring full functional coverage and quality sign-off Responsibilities: 1.Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. 2.Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. 3.Working with project management and leads on planning tasks, schedules, and reporting progress 4.Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Qualifications: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering 4+ years of relevant experience in CPU or SoC-level functional verification Interested can CV to sharmila.b@acldigital.com

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. This position involves System Verilog real number modeling and functional verification of blocks involved in WAN, GPS radios for 5G products. Roles and responsibilities include: Understanding device functionality, building verification plan, functional Modeling of analog blocks in System Verilog, running and debugging testcases on a large mixed-signal SOC on RTL and Gate Level Netlists. Setting up and running AMS testbenches for RFIC modules. Working with SPICE/Spectre simulators and digital simulators (co-simulation). Analysis and debug Analog circuits. UVM/SV based Testbench creation, verification, creating self-checking tests, regression, debug, coverage analysis, bug tracking Scripting using PERL/Python/Shell to automate day to day verification tasks Working with Analog and Digital design environments like Cadence ncsim, simvision, virtuoso. Working in a fast paced environment with Analog, Digital design/DV, DFT engineers to ensure complete SoC verification Post silicon bringup support Minimum Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering or related field, Masters preferred 2+ years ASIC design, verification, or related work experience Preferred Skills Experience in the following skills: Electrical circuit analysis Verilog, SystemVerilog, UVM Perl or Python Phaselock loops, ADCs, DACs, and serial programming interfaces Writing behavioral models of analog blocks including event driven simulator Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 10+Yrs of exp #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience with Verilog or System Verilog Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization Preferred Qualifications 15+ years of experience in silicon development Experience in data path development Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems Experience in HLS (High-Level Synthesis) Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) Experience working across multiple projects About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities: We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to create new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards chipping in to your success. We Are Not Looking for Superheroes, Just Super Minds! We’ve got quite a lot to offer. How about you? Required Experience: We seek a graduate with at least 5+ years of relevant working experience with B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. Proficiency of C/C++, algorithm and data structures. Compiler Concepts and Optimizations. Experience with UNIX and / or LINUX platforms is vital. Basic Digital Electronics Concepts We value your knowledge of Verilog, System Verilog, VHDL Experience in parallel algorithms, job distribution. Understanding of ML/AI algorithms and their implementation in data-driven tasks Exposure to Simulation or Formal based verification methodologies would be a plus! The person should be self-motivated and can work independently. Should be able to guide others, towards project completion. Good problem solving and analytical skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #DVT

Description Invent the future with us. Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us. About The Role You will work on the verification of a server-class microprocessor-based CPU/Coherent Mesh interconnect. You'll be involved with all aspects of pre-silicon verification at unit and system level to ensure functional correctness and performance of microprocessors. You'll also partner with other teams to accelerate post-silicon validation and debug of the product. In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power. What You’ll Achieve Define requirements for block level and subsystem level testing infrastructure Create test plans for unit-level and chip-level verification and post-silicon validation Architect, design and implement test benches and other components of design verification environment Create random test generators to find bugs in design Debug failures and drive speedy resolution of bugs Create coverage monitors and drive coverage to required quality targets Define post-silicon validation plans, and engage in post-silicon activities to accelerate product launch Lead verification activities within a team and guide other engineers to achieve project goals About You M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience Solid understanding of high-performance microprocessor architecture concepts Experience using industry standard HDL languages (Verilog, System Verilog, VHDL) and simulation tools Experience developing verification environments in one or more industry standard languages like SVTB UVM/OVM Programming experience in languages common to the industry (e.g., C, C++, Perl, Python) Experience in automating design, verification, and validation tasks Hands on experience in post-silicon validation Knowledge of ARM or x86 architecture and assembly language programming Previous experience in CPU/core design verification is preferred Previous experience in Network-on-chip (NoC) design verification is preferred Previous experience with Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols is preferred Previous experience with formal verification is preferred What We’ll Offer At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits Highlights Include Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience. 4 years of experience in RTL coding. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs. Experience with ASIC design methodologies for clock domain checks and reset checks. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The gChips team develops custom silicon solutions that provide differentiated user experiences in Google Hardware products and optimize performance and power for the aimed use cases. This includes SoCs (systems on a chip) and other mixed signal, logic, and sensor ICs (integrated circuits) for our product portfolio. Working with the product teams and other teams throughout Google, gChips maps out the silicon requirements looking ahead two to four years. In addition, it ensures the Hardware Product Area is up-to-date on the latest chip technologies and CPU, IO and memory standards. In this role, you will be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, RTL, low power design methodology and evaluate design options with performance, power and area. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Collaborate with architects and develop microarchitecture. Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks. Develop RTL implementations that meet engaged power, performance and area goals. Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up. Travel to other sites across the world to collaborate with global teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

We are seeking highly motivated and talented VLSI Engineers with 2-4 years of industry experience to join our intensive Campus Training Program. This program is designed to provide in-depth, hands-on training in various aspects of VLSI design, verification, and implementation, specifically tailored to align with our current projects and future technological advancements. Upon successful completion of the training, candidates will transition into key roles within our VLSI design teams. This is an excellent opportunity for engineers looking to deepen their expertise, specialize in cutting-edge VLSI methodologies, and contribute to the development of next-generation semiconductor products. Responsibilities during the Training Program: * Actively participate in structured training modules covering advanced VLSI concepts, methodologies, and tools. * Engage in hands-on lab sessions and practical exercises to apply learned concepts. * Collaborate with trainers and mentors on assigned projects and case studies. * Complete individual and group assignments, demonstrating understanding and proficiency in VLSI sub-domains. * Participate in technical discussions, design reviews, and knowledge-sharing sessions. * Learn and adhere to industry best practices, design flows, and quality standards. * Continuously seek to improve technical skills and knowledge through self-study and provided resources. * Document progress, learning outcomes, and project work thoroughly. Key Areas of Training (may include, but are not limited to): * Digital IC Design: Advanced RTL design, low-power design techniques, clock domain crossing (CDC). * Verification: Advanced UVM/SystemVerilog methodologies, functional coverage, formal verification. * Physical Design: Floorplanning, placement, routing, clock tree synthesis (CTS), static timing analysis (STA), power integrity (PI) analysis. * Design for Testability (DFT): Scan insertion, ATPG, boundary scan. * Analog/Mixed-Signal Design (if applicable): Device physics, circuit simulation, layout considerations. * Front-End Tools: Synthesis, Linting, STA. * Back-End Tools: Place and Route, DRC/LVS. * Scripting: Perl, Python, TCL for automation. * EDA Tools: Exposure to industry-standard EDA tools from Cadence, Synopsys, Mentor Graphics (specific tools will be taught based on company needs). Required Qualifications: * Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering (EE), or a related field. * 2-4 years of professional experience in VLSI design, verification, or physical design. * Strong fundamental understanding of digital electronics, circuit theory, and semiconductor physics. * Proficiency in at least one hardware description language (HDL) such as Verilog or VHDL. * Familiarity with the VLSI design flow (front-end to back-end). * Experience with scripting languages (e.g., Python, Perl, TCL) is highly desirable. * Excellent problem-solving and analytical skills. * Strong communication and interpersonal skills. * Ability to learn quickly and adapt to new technologies and methodologies. * Self-motivated with a strong desire to build a long-term career in VLSI. Preferred Qualifications (Assets): * Prior experience with specific EDA tools (Cadence Virtuoso, Synopsys DC/ICC/VCS, Mentor Graphics Calibre, etc.). * Experience with UVM methodology for verification. * Understanding of low-power design techniques. * Familiarity with formal verification concepts. * Exposure to advanced technology nodes.

At Electronix.AI, we’re building tools for the engineers of tomorrow, tools that understand, automate, and accelerate the hardware development cycle. Website : Electronix AI | Accelerate Hardware Design Decisions We are now looking for an AI Full-stack Engineering Intern to join our team! This is your opportunity to be part of a fast-paced startup building AI-powered tools for the hardware world. You'll work with people who value autonomy, rapid prototyping, and deep problem-solving, and you'll help shape systems used in the field, not just in the cloud. ⚡What You’ll Be Doing (Responsibilities): Develop and optimize backend services using Python (FastAPI, HuggingFace Transformers, OpenCV). Design and deploy APIs for AI-powered automation, video analytics, and search applications. Develop and deploy robust on-premises solutions that integrate seamlessly with existing infrastructure. Implement and manage DevOps pipelines, ensuring continuous integration and deployment workflows across cloud and on-prem environments. Ensure scalability, security, and reliability across infrastructure and applications. Work with databases and caching layers like MySQL, Elasticsearch, Redis, and Vector DBs (Qdrant, ChromaDB, etc.). Develop frontend components using TypeScript, React, and GraphQL to create intuitive user experiences. Troubleshoot and resolve complex system performance issues, particularly for on-prem deployments and high-performance computing environments. (Nice to Have) Experience with Kubernetes for container orchestration ⚡ What we need to see: Backend : Python (FastAPI, HuggingFace Transformers, OpenCV), MySQL, RabbitMQ, GraphQL Front-End: React, TypeScript AI & Search: Elasticsearch, Redis, Vector DBs (Qdrant, ChromaDB) Cloud & DevOps: Docker, AWS, Azure, CI/CD, On-Prem Deployments Bonus : Kubernetes, GPU-based workloads (NVIDIA GPUs preferred) ⚡ Internship Details: Duration : 4-6 months Location : Onsite/Hybrid (min 3x a week) - Bengaluru (Jayanagar/Richmond Town) Stipend : Monetary compensation included. Additional Perks : Early access to product decisions, real-world deployment experience, high ownership. ⚡ Good to Have: These are extras that help us spot naturally curious, hands-on builders. None are hard requirements especially the hardware items, which are purely optional bonuses. Hands-On AI Exploration: Personal / academic projects showing end-to-end use of modern AI stacks—e.g., fine-tuning or serving models with Hugging Face Transformers, building RAG pipelines, or experimenting with OpenAI, Gemini, or Ollama APIs. Evidence you can move beyond tutorials: custom data pipelines, evaluation scripts, or deployment artefacts that solve real problems. Tooling & Framework Depth Comfort with open-source LLM toolchains such as LangChain, LlamaIndex, FastEmbed, or Haystack. Experience running or optimising models on GPU/CPU edge devices; bonus points for on-device inference tricks (quantisation, pruning, TensorRT, ONNX, GGUF). Familiarity with vector databases (Qdrant, Chroma, Weaviate) and search frameworks (Elastic, OpenSearch). (Optional Bonus) Hardware-Aware Mindset : Purely a plus, great if you have it, absolutely fine if you don’t. Basic exposure to the semiconductor / EDA landscape, PCB design, or HDLs (Verilog/VHDL). Past tinkering that bridges software with sensors, FPGAs, Raspberry Pi, Jetson, or lab equipment. Appreciation of constraints unique to on-prem or embedded deployments: latency, memory, thermals and how they influence architecture. MLOps & Dev-Infra Curiosity Initial exposure to MLOps concepts: experiment tracking (Weights & Biases, MLflow), model registry, automated evaluation. Comfort scripting IaC with Terraform/Ansible or writing GitHub Actions to ship prototypes rapidly. Show-Don’t-Tell Proof An active GitHub with readable READMEs, issues, and commit history reflecting iterative learning. Blog posts, lightning talks, or demo videos explaining challenges, trade-offs, and learnings. Clear communication counts. Contributions : big or small, to open-source projects in AI, DevOps, or hardware realms. ⚡ Personal Traits We Value: Relentless curiosity: you ask why and keep digging. Bias for rapid prototyping: build, test, iterate. System thinking: see the whole stack and optimize the right layer. Collaborative clarity: explain complex ideas simply and receive feedback constructively. Bring tangible evidence: code, designs, write-ups, documentation - showcasing how you learn and build. We’re excited to see what you’ve been tinkering with! ⚡ Hiring Process: GitHub Review Profile Shortlisting Technical Task/Assignment Deep Dive Interview Join the Team!

Job Description Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints Additional Information Soft Skills and Cultural Fit Strong communication skills to articulate design concepts and collaborate with multi-disciplinary teams Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.