2321 Verilog Jobs - Page 37

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

- Lead the architecture, design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems. - Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Instruction Dispatch unit of CPU - Hands of experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of Instruction Decode and Execution units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Required technical and professional expertise . 6 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise .12 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

In this role, you are expected to Develop algorithms in C/C++ for circuit characterization tools critical to develop standard cell libraries. Develop applications using the latest Web technologies (javaScript,AngularJS,HTML) for tool-front end. Have excellent debugging skills Build knowledge of Library characterization Have strong interpersonal skills needed to coordinate deliverables and requirements from several areas within and outside of the organization. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 2-5 years years of soft ware programming experience Strong C/C++programming skills in a Unix/Linux environment are desired. VLSI knowledge, Knowledge in Standard Cell Power Modelling/ Power Domain. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must EDA tool development experience Preferred technical and professional experience Cadence, VLSI knowledge, VHDL/Verilog, computer architecture, Machine Learning/AI.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Lead the architecture, design and development of Processor Core Load- Store Execution unit for high-performance IBM Systems. - Architect and design Load and Store pipelines, D-Cache, Address Translation, Out of Order Execution of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Load-Store Execution unit of CPU - Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and Arithmetic units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred Education

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: o Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. o Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results o FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. o Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. o Be an effective contributor in a cross-functional team-oriented environment. o Write high quality code in Verilog, VHDL and C code for embedded processors. Maintain existing code. o Learn new system designs and validation methodologies. Understand FPGA architectures. o Be conversant with on-chip debug tool Requirements/Qualifications: Qualifications/Requirements Excellent verbal and written communication skills in English 2+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios Optimizing code for FPGA architectures Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE Working knowledge on embedded software C/C++ is also a plus Strong technical background in FPGA prototype emulation, and debug Strong technical background in silicon validation, failure analysis and debug Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal Design with RTL coding in Verilog and VHDL is a must Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: i. PCIe Gen1/2/3 ii. Interlaken (10.3125 Gbps) iii. CPRI (614.4Mbps 12.672 Gbps) iv. SGMII or QSGMII v. XAUI or HiGig/+/II vi. 10GBASE-R/-KR vii. Serial Rapid IO Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Job Title - RTL Design Engineers Exp Level: 4+ yrs Loctaion: Hyderabad /Bangalore Job Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge • Tools knowledge: Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC 0in Formality and conformal LEC tool • Design and scripting languages: Verilog and SV Perl Python TCL Interested can share CV to sharmila.b@acldigital.com

Experience Level:5+ years of RTL design and development Location: Hyderabad/Bangalore Job Description:Silicon Design Engineer Basic Job Deliverable:Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification, design, user-guide, etc., o Experience:  Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools  Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc.  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) Interested can share CV to sharmila.b@acldigital.com

Experience Level:5+ years of RTL Verification Location: Hyderabad/Bangalore Job Description:Hardware Verification Engineer Basic Job Deliverable:HW Verification Engineer o Responsible for RTL verification, developing Develop SV/UVM testbenches at Top/Sub-system/Block-levels. o Responsible for driving test plan and test spec development and execution, generating documents, such as user-guide, test plan, test spec, test report etc., o Engaging in verification environment architecture and methodology development. o Experience:  Experience in System Verilog and UVM programing  Experience with verification of protocols like Ethernet/PCIe/SPI/I2C/USB  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Experience with Xilinx technology and tools, FPGA verification and test  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Qualification:B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Interested can share CV to sharmila.b@acldigital.com

CENTUM T&S, headquartered in France, is a business unit of Centum Electronics Group (Around 1000Cr turnover organization) offering a wide range of electronic and embedded systems design engineering services to international customers to help them realize complex products and sub systems. It includes design, development, qualification, value engineering, testbench design & manufacturing and many more services. Centum T&S has established its India operations in North Bengaluru, known as Centum T&S Pvt Ltd (CTS), formerly known as Centum Adeneo India Pvt Ltd. CTS is working with many top companies like Airbus, Thales, Hitachi Energy, GE, ABB, DANA, Alstom, etc., The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skill FPGA Extended team is composed of 8 engineers in India (Bangalore) & 8 engineers in France (Lyon). FPGA manager is the responsible for the FPGA team competences and directly report to the Chief Technical Officer. Position can either be in India Bangalore or in France Lyon The manager will know the unique skills and experience of the FPGA development group. The manager should be familiar with current FPGA designs in use in client products and collaborate with key resources, leveraging existing FPGA design work when possible. For a new development cycle, the manager will work with others to develop system architecture diagrams to ensure adequate information is available when beginning the project. The manager will lead the team through the process of understanding the requirements, creating additional diagrams as needed to support the development cycle. Managing FPGA development requires knowledge of Xilinx products and development tools, within aeronautical domain The manager will be responsible for finding the new engineering talent needed to support the needs of Clients products. The manager will mentor team members and contribute to their career development, learning and assuming tasks laid out in this job description. What You'll Do Manage FPGA Team composed of 8p in France and 8p in India. Hire and support the FPGA engineers, including project leads, working programs within the portfolio .Lead or contribute to individual programs and support new business and proposals for the department, including architecture development and the selection of appropriate technologies to meet mission requirements. Train and mentor less experienced engineers and project leads while building effective teams. Design and implementation of FPGAs collaborating with peer engineers and global stake holders Participate in the architecture definition Provide reliable estimates for the work to be performed and identify technical risks Ensure performance with expected quality and within schedule; achieve and surpass the productivity norms of the global organization, driving continuous improvement Key values, beliefs, and at Attitudes Results-orientation: Focus on Customers, provide quality deliverables on time, within estimated effort with high-quality Characteristics for a design engineering services business: establish trust, responsive to change/adaptability; learn continuously, proactive, positive & joyful . Who You Are? Bachelor's degree in Computer Science, Electrical OR Electronics Egg (or related field)10 to 15 years of experience in FPGA designs 5 years in the aeronautical domain, following DO254 process Strong knowledge in RTL(FPGA/SOC/IP) design architecture & design; Coding experience in VHDL or Verilog. UVM Experience is added advantage. 10+ years)Experienced in PCI Express, 1G/10G Ethernet or SERDES high-speed serial links, AXI/AHB, I2C, SPI, RS422, ARINC 429/717/818, MIL 1553 etc Experience in memory control interfaces such as Flash, DDR2/3, etc. Expertise in troubleshooting and debugging FPGA implementation Experience in building test benches and bus functional models for FPGA simulation Experience in writing scripts to drive simulation and synthesis tools Excellent documentation, reporting and communicate on skills. Excellent analytical skills.

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys/Block Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Experience: Bachelor s degree in CS/EE with 8 12 years of relevant experience, or Master degree in CS/EE with 8 10 years of relevant experience Strong background in IP, Subsystem and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Job Description Summary Lead FPGA Engineer will be responsible for leading/executing complex FPGA design projects and solutions. You will work in a global environment with skilled team of engineers creating and improving a state-of-the-art platform for use in every kind of power generation application Job Description Essential Responsibilities Select the FPGA, CPLD family and chip suitable for the application. Develop FPGA design requirements based on system requirements document. Define FPGA interfaces with other circuitry along with hardware design engineer. Do FPGA programming, synthesis and simulation, timing analysis and optimization. Validate system along with the hardware and firmware design engineers to confirm about functionality, reliability, efficiency, compatibility and responsiveness. Work on FPGA-based solutions for interfacing real-time microprocessor systems to high speed Networks and I / O Actively drive design rigor and participate in relevant formal design reviews Contribute to board level reliability analysis and system FMEA Identify opportunities to modify/author DPs Identify cost-out opportunities and make technical proposals Lead/ Participate on teams assigned to address organizational initiatives. Qualifications/Requirements Bachelor / Masters in Electronics Engineering, Electronics & communication, Computer Engineering or equivalent. 8-10 years of experience in FPGA design, digital circuit design, system level analysis, Product Development life cycle including system and Sub-system Design Proven analytical and organizational ability Strong interpersonal and leadership skills Strong oral and written communication skills Effective problem identification and solution skills Desired Characteristics Hands on experience in Verilog, VHDL, FPGA development tools, including design, synthesis, simulation, timing analysis, optimization, packaging and debug Expertise in Signal Integrity and simulations Knowledge about different communication techniques Hands on experience in developing the interfaces between FPGA and other devices like microprocessors, ADCs, transceivers and so on. Strong experience of High-speed digital designs, Proficiency in ECAD suite of tools either from Mentor Graphics or Cadence would be an added advantage. Should have a good understanding of EMI/EMC concepts related to high speed designs and debug issues. Experience working with Industry protocols like MODBUS, FF,CAN, Ethernet Ability to coordinate several projects simultaneously. Experience in Agile methodology. Additional Information Relocation Assistance Provided: Yes

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities: We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to create new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards chipping in to your success. We Are Not Looking for Superheroes, Just Super Minds! We’ve got quite a lot to offer. How about you? Required Experience: We seek a graduate with at least 5+ years of relevant working experience with B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. Proficiency of C/C++, algorithm and data structures. Compiler Concepts and Optimizations. Experience with UNIX and / or LINUX platforms is vital. Basic Digital Electronics Concepts We value your knowledge of Verilog, System Verilog, VHDL Experience in parallel algorithms, job distribution. Understanding of ML/AI algorithms and their implementation in data-driven tasks Exposure to Simulation or Formal based verification methodologies would be a plus! The person should be self-motivated and can work independently. Should be able to guide others, towards project completion. Good problem solving and analytical skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. #DVT

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a Design Engineer-2 FPGA Architecture to join the Architecture team focused on FPGA architecture modeling and advance system architecture. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in architecture modeling and evaluation of Lattice FPGA’s and Software tools to measure performance, power, and area for various workloads The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with Software tools team to define benchmarks, measure performance and suggest improvement areas Serve as a technical expert, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and open-minded student Accountabilities Serve as a key contributor to build FPGA architecture modeling and evaluation platform efforts Drive logic design of key FPGA workloads and bring best-in-class methodologies to accelerate design and test time and quality. Develop the regression testing framework to execute, measure and report architecture modeling and evaluation experiments Ensuring design quality throughout project development conducting regular reviews and audits Perform architecture evaluation of competitive products Work with cross functional team including program management, Software Tools, HW architects, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up to date with the latest industry trends and technologies Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 3+ years of experience in driving logic design across a multitude of FPGA projects. Expertise in FPGA designs, use-cases, and design considerations, defining micro-architecture and experience of working with various EDA tools Experience in leading the project throughout design cycle and working with cross organization Proven ability to work with multiple groups across different sites and time zones. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The role will focus on RTL design and full chip integration and projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc. The role requires to work with architect and micro-architect team to understand define design specifications The successful candidate will be open and willing to both (a) teach best-known-methods to an existing design team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and an open-minded student. Accountabilities Serve as a key contributor to RTL design efforts. Drive logic design of key blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality through assertions, checkers, and scripting. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 5+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus. Familiarity with FPGA designs, use-cases, and design considerations is a plus. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Noida Job ID: SS202500078 Function: Desinger Role: CircuitDesigner Desired Skills: Analog circuit design, EDA, circuit simulation, layout porting, and analog front-end development Job Description 🔧 What You’ll Bring: ✔️ B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or Physics ✔️ 5+ years of hands-on experience in analog circuit design and EDA tools ✔️ Strong command over circuit simulation, layout porting, and analog front-end development ✔️ Excellent communication & coordination skills ➕ Bonus: Exposure to Verilog-A or C programming 🚀 What You’ll Do 🔹 Develop and support new design/technology porting flows 🔹 Collaborate with PDK, Modeling, and Device teams 🔹 Enable and validate schematic layout porting, set up analog simulations, and ensure performance accuracy 🔹 Drive tool improvements and optimize existing migration workflows 📩 Interested? Send your updated resume along with the below details to: 📧 aayushi.sharma@saracasolutions.com | 📧 sanjay@saracasolutions.com 📝 Required Details (India) Total years of experience Notice period Current location and hometown Current CTC and expected CTC Reason for change Offer in hand (if yes, please share details) Are you willing to relocate? What are your primary skills? Looking forward to connecting with great talent!

90/130/150nm and higher node with PMIC layout experience. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective actions if needed until result is successful Performs layout in such a way that final result meets the foundry layout rules. Provides extracted netlist for back annotation to DE as specified in the Design document, section layout. Translates sub block schematics to sub block layouts, taking care of the same hierarchical build-up and respecting the guidelines of the Block review document, section layout. Adds extra useful information to the Block review document, section layout.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled R&D Staff Engineer passionate about pushing the boundaries of static low power verification products. With 5 to 8 years of experience in software engineering, you have honed your expertise in C/C++ and possess a robust understanding of data structures and algorithms. Your background in Electronic Design Automation (EDA) tools and methodologies, coupled with your knowledge of Verilog, SystemVerilog, and VHDL, positions you as a leader in your field. You are a proactive problem-solver with a keen eye for detail, and you thrive in collaborative environments where you can lead and inspire a team. Your self-motivation and discipline drive you to set and achieve personal goals consistently, and your commitment to quality ensures that your contributions make a significant impact. Based in Noida or Bangalore, you are ready to take on new challenges and help shape the future of technology. What You’ll Be Doing: Designing and developing state-of-the-art EDA tools with innovative algorithms. Collaborating with local and remote teams to ensure seamless integration and execution. Working directly with customers to understand requirements, provide online debugging, and track delivery and execution. Leading a small team of 2-3 members, guiding them through technical challenges and project milestones. Contributing to the continuous improvement of our static low power verification product. Exploring new architectures and leading the charge in developing cutting-edge solutions. The Impact You Will Have: Driving the development of advanced EDA tools, contributing to the efficiency and effectiveness of chip design. Enhancing the quality and reliability of our static low power verification product. Providing critical support to customers, ensuring their needs are met and fostering long-term relationships. Leading and mentoring junior engineers, fostering a culture of innovation and excellence within the team. Contributing to Synopsys' reputation as a leader in the semiconductor and EDA industries. Playing a pivotal role in the successful execution of projects, meeting deadlines, and exceeding expectations. What You’ll Need: Fluency in C/C++ with a strong background in data structures and algorithms. Experience with UPF and familiarity with Tcl and Python-based development on Unix (preferred). Knowledge of Verilog, SystemVerilog, and VHDL HDL (preferred). Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Who You Are: You are a dynamic and innovative engineer with a passion for technology and a commitment to quality. You possess excellent problem-solving skills and the ability to think critically and creatively. As a self-motivated individual, you set personal goals and work diligently to achieve them. Your leadership skills enable you to guide and inspire your team, fostering a collaborative and productive work environment. You are detail-oriented, ensuring that your work meets the highest standards of quality and reliability. Your experience in EDA tools and methodologies, coupled with your knowledge of hardware description languages, positions you as a valuable asset to our team. The Team You’ll Be A Part Of: You will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing our static low power verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, you will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Skills Required: Strong technical foundation and proven hands-on experience in VLSI, FPGA & VERILOG Ability to guide students in the technologies mentioned. Must be able to confidently explain and simplify complex VLSI, FPGA, VEERILOG concepts for diverse age groups and academic levels. Excellent communication skills in English and Hindi (both verbal and written). Strong planning and time management abilities. Strong public speaking and presentation skills. Comfortable handling large groups and tailoring delivery methods to suit different institutions. Excellent stakeholder management handling clients, academic institutions, and internal teams. Willingness to take up training responsibilities as required. Role & responsibilities Lead Training Sessions: Deliver engaging and practical training sessions covering VLSI , FPGA Development , Verilog HDL, Digital System Design across colleges, schools, and premier institutions . Mentorship & Team Training: Train, guide, and mentor junior trainers from PHN Technology, ensuring content and delivery consistency in VLSI, FPGA, and Verilog. Content Development: Develop and continuously update training materials, live projects, lab exercises, and demos that provide hands-on experience with VLSI design concepts and FPGA implementation. Travel Readiness: Willingness and ability to travel extensively across India for conducting workshops and sessions as per schedule. Preferred candidate profile We are looking for a highly skilled professional with deep expertise in VLSI , FPGA Development , Verilog HDL, Digital System Design The ideal candidate should have a minimum of 5+ years of relevant experience in teaching, corporate training, or industry roles. A strong command over communication (both verbal and written) in English and Hindi is essential, along with the ability to clearly explain and simplify complex concepts to learners across diverse age groups and academic levels. Candidates should possess excellent public speaking and presentation skills , and be comfortable delivering sessions to large groups while tailoring the content as per institutional needs.

Title: Principal Engineer, Design Enablement Modeling About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Perform model extractions for DC and RF frequencies for devices like Diodes, Varactors, Resistors, ESD etc. and develop a compact model based on device physics for SOI, Bulk technologies. Responsible for the definition of test structures and layouts for the necessary devices and submit tests like DC-CV, DC-IV, S-parameters, Noise, Mismatch etc. for electrical characterization. Work closely with team members and interact with global team to understand and solve any discrepancies in data or model. Your Job: Interact with the Technology Development, Measurement Lab and Library (LVS, PEX) Teams to understand the flow right from the Process through Design, Hardware measurements and modeling aspects. Use modeling tools like Cadence and Simulators (Spectre and HSPICE) and Verilog-A for model parameter extraction and testing. Device model extraction for DC and RF frequencies (BEOL capacitor, Inductor, Diode, Varactor, Resistors, ESD device etc.). Definition of test structures and layout as and when necessary. Knowledge of semiconductor physics and application in understanding device data, especially passive devices. Knowledge of S-parameters and their application in extracting device models. Interaction with team to resolve discrepancies in the data, model etc. RF knowledge of Back-end of line devices like Inductors, Capacitors, Transmission Lines. Able to analyze and debug EM simulations. Characterize and Model various Back end of line devices. Address/debug customer issues that may arise from time to time. Explore innovative solutions to challenging problems at work and file patents as well as publish quality work in reputed peer reviewed journals and conferences. Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Required Qualifications: Education Masters/Ph.D in Electronics, VLSI, Semiconductor Physics or related field. Years of Experience Freshers with suitable background may apply Fluency in English Language - written & verbal Preferred Qualifications: Strong background in Semiconductor Device Physics, Circuit level appreciation and moderate experience with ICCAP, ADS, Verilog-A and scripting languages like Python, R. Knowledge in RF and EM simulation is a plus (S-parameters etc.). Experience in semiconductor device characterization is a plus. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. To ensure that we maintain a safe and healthy workplace for our GlobalFoundries employees, please note that offered candidates who have applied for jobs in India will have to be fully vaccinated prior to their targeted start date. For new hires, the appointment is contingent upon the provision of a copy of their COVID-19 vaccination document, subject to any written request for medical or religious accommodation.

Title: Principal Engineer, Design Enablement Modeling About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: Perform model extractions for DC and RF frequencies for devices like Diodes, Varactors, Resistors, ESD etc. and develop a compact model based on device physics for SOI, Bulk technologies. Responsible for the definition of test structures and layouts for the necessary devices and submit tests like DC-CV, DC-IV, S-parameters, Noise, Mismatch etc. for electrical characterization. Work closely with team members and interact with global team to understand and solve any discrepancies in data or model. Your Job: Interact with the Technology Development, Measurement Lab and Library (LVS, PEX) Teams to understand the flow right from the Process through Design, Hardware measurements and modeling aspects. Use modeling tools like Cadence and Simulators (Spectre and HSPICE) and Verilog-A for model parameter extraction and testing. Device model extraction for DC and RF frequencies (BEOL capacitor, Inductor, Diode, Varactor, Resistors, ESD device etc.). Definition of test structures and layout as and when necessary. Knowledge of semiconductor physics and application in understanding device data, especially passive devices. Knowledge of S-parameters and their application in extracting device models. Interaction with team to resolve discrepancies in the data, model etc. RF knowledge of Back-end of line devices like Inductors, Capacitors, Transmission Lines. Able to analyze and debug EM simulations. Characterize and Model various Back end of line devices. Address/debug customer issues that may arise from time to time. Explore innovative solutions to challenging problems at work and file patents as well as publish quality work in reputed peer reviewed journals and conferences. Other Responsibilities: Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Required Qualifications: Education Masters/Ph.D in Electronics, VLSI, Semiconductor Physics or related field. Years of Experience Freshers with suitable background may apply Fluency in English Language - written & verbal Preferred Qualifications: Strong background in Semiconductor Device Physics, Circuit level appreciation and moderate experience with ICCAP, ADS, Verilog-A and scripting languages like Python, R. Knowledge in RF and EM simulation is a plus (S-parameters etc.). Experience in semiconductor device characterization is a plus. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia