2321 Verilog Jobs - Page 39

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Job Description: We are looking for a RTL Design Engineer with expertise in SoC and IP-level design and integration. The ideal candidate should have a strong background in RTL coding, architecture-level understanding, and industry-standard quality checks and tools. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog Understand and apply top-level SoC architecture concepts Perform SoC and IP-level integration Implement RTL quality checks including CLP (mandatory), LINT, CDC, RDC, VSI Work on design partitioning (Tilification) Handle IORING, PHYs, GPIOs Collaborate with verification and backend teams Required Skills: RTL coding in Verilog and SystemVerilog IPXACT knowledge Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) UPF and SDC concepts Tools: VC_static, SpyGlass (Lint, CDC, RDC), 0in, Formality, Conformal LEC Scripting: Perl, Python, TCL Nice to Have: Experience with design quality metrics and standards Exposure to physical-aware RTL design

About the Company Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. About the Role Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Responsibilities Own end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Design Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 5+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 10+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: 7 to 12 years of experience, mainly in design Experience in Verilog and/or SystemVerilog Working experience of AMD/Xilinx FPGA and Vivado Experience in Video domain (DisplayPort/MIPI) is preferred Candidate shall be working AMD Sattva site, Hyderabad. TekWissen Group is an equal opportunity employer supporting workforce diversity.

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors 6. Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives 7. Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization 8. Stakeholder influencing and people skills must be excellent. 9. Needs to be able to set aggressive goals and manage risks effectively 10. Must have a thorough understanding of tool development methodology. 11. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. 12. MS or Ph.D. Engineering degree (EE or equivalent) with 3-7 years semiconductor industry experience.

Job Description: Minimum of ten years of hands-on Test Development experience (DFT, EDA tools, etc..) Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system Strong planning, project, and people management skills required. Must have experience developing managers and individual contributors Experienced hands-on technical manager not afraid to dig into details to provide technical direction Proven track record of delivering results and meeting quality, cost, and time-to-market objectives Ability to collaborate with overseas colleagues to define strategy, plan, and execute across the larger, global organization Stakeholder influencing and people skills must be excellent. Needs to be able to set aggressive goals and manage risks effectively Must have a thorough understanding of tool development methodology. Ability to manage software development tasks associated with specifying, developing, scheduling, and debugging according to current and future tool requirements. MS or Ph.D. Engineering degree (EE or equivalent) with 3-10 years semiconductor industry experience.

Looking for Platform/Board Design Engineers with the following requirements and this is an immediate requirement. Extensive experience in hardware board design. Strong foundation and expertise in analyzing digital, Analog and power electronic circuits. Proficient with AMD FPGAs, CPLD and MPSOC architecture-based board designs. Knowledgeable in signal integrity, EMI/EMC concepts for digital and power electronics. Completed at least one project from high-level design to final product level validation. Capable of independently handling schematic Capturing, design analysis DC Drop, Singal Integrity, and coordinating reviews with peer of layout, mechanical, SI, and EMC teams. Experienced in board bring-up, issue investigation, and triage in collaboration with firmware and software teams. Skilled in preparing hardware design documentation, validation test planning, identify necessary test equipment, test development, execution, debugging, and report preparation. Effective communication and interpersonal skills for collaborative work with cross-functional teams, including post-silicon bench validation, BIOS, and driver development/QA. Experience with server platforms and ATX-based complex HDI board designs s is a plus. Hands-on experience with Cadence Allegro/Altium EDA tools is essential. Familiarity with programming and scripting languages like Python and Perl, and experience in test automation is advantageous. Education Requirements: B. Tech/B.E./M. Tech/M.E. Experience: 5 to 10 Years Location: Hyderabad Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Experience : 3 to 10 Years Qualification : Bachelors or Masters (Electronics and Communication Engineering or equivalent) Job Description: As an Emulation Engineer, youll be an integral part of a dynamic team dedicated to creating cutting-edge ASIC solutions for High-Performance Computing (HPC) systems. Your role will involve defining the validation strategy leading to functional sign-off for these high-performance computing designs. Key functions and responsibilities: Proficient in various emulation technologies, including simulation acceleration, in-circuit emulation, speed bridges, virtual prototyping, and hybrid methods. Familiarity with tools such as Palladium, Protium, Veloce, or Zebu. Good Knowledge of SystemC/C/C++ and UVM/SV verification languages Experience with SystemVerilog and C++ for modelling RTL components and transactors. Ability to develop C/C++/SystemC/SV tests in HDL-HVL (Hardware Description Language-Hardware Verification Language) Co-emulation platforms. Understanding of compilation and build flow. Skilled at building images from scratch, making necessary design modifications to adapt to emulation. Work closely with verification teams to define and implement comprehensive pre and post silicon test plans. Interface effectively with design, verification, validation, and software development teams to understand their needs from an emulation perspective. Experience in architecting emulation systems for various design scales (IP blocks, SOC, multi-chip systems). Balancing performance and ease of debug. Proficient in post-silicon bring-up, debugging, and issue reproduction on emulators. Familiarity with Python and TCL scripting languages. Exposure to domains such as PCIe, CXL, DDR, Flash, Memory, USB, and CPU. Strong communication and collaboration skills to work effectively with cross-functional teams and domain experts. Successfully manage multiple design releases and provide support for debugging customer issues.

SMTS SILICON DESIGN ENGINEER PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 13+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

MTS GFX Design Role: We are currently seeking a highly skilled design engineer for GFX Design team. Responsibilities: In this role, he/she would be responsible for verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Working with all partners such as lead architects and block design teams to understand features to be implemented and verified. Developing robust test plan for both synthetic testing and real workload trace Debug verification test failures, working with the verification team to accurate defects. Make sure AMD next generation GFXIP can meet performance/power/function expectation. Requirements: Must have Min 8 years of experienced in ASIC verification. Must be proficient in Verilog and System Verilog language Must be good at optimizing timing in digital design. Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and develop optimal microarchitecture specification that meets PPA goals. Be proficient of script language like Perl, Python. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics pipeline experience is preferred. Good knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required. Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 8+ Years of Exp Location: Bangalore, India #LI-NS1 Benefits offered are described: AMD benefits at a glance .

THE ROLE: AMD is looking for a s enior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for S oftware engineering development , and is diligent and passionate about Technology . A successful candidate will need to employ strong knowledge in computer technologies, leadership skills in technical areas, and SW engineering expertise as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators. KEY RESPONSIBILITIES: Develop and drive execution of comprehensive , highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team C ollaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results PREFERRED EXPERIENCE: Strong digital design and simulations basics RTL (VHDL, Verilog & System Verilog) coding skills Understanding of FPGA design flow and tools (Synthesis, Simulation and implementation) ASIC/FPGA verification experience VHDL and Verilog Xilinx Vivado Design Suite experience Hands on experience on simulators like XSIM, Questa, Modelsim, VCS etc. Advanced Debug skills in software environment or strong problem-solving skills Hands on experience with scripting preferably tcl, pearl and python ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer/Software Engineering, Computer Science, or related technical discipline #LI-NR1 Benefits offered are described: AMD benefits at a glance .

SOC Emulation Lead: THE ROLE: As an Emulation Verification Engineer in AMD s Server SoC team, you ll be at the forefront of validating next-generation server-class SoCs using advanced emulation platforms. Your mission: ensure AMD s silicon hits the ground running bug-free, high-performance, and server-grade reliable. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Bring-up and debug of large SoC designs on emulation platforms (e.g., Palladium, Veloce, Zebu). Develop and execute test plans to validate functionality, performance, and power on emulators. Create and integrate monitors, checkers, and assertions in SystemVerilog/UVM environments. Collaborate with cross-functional teams including RTL design, architecture, firmware, and post-silicon validation. Analyze failures, root-cause bugs, and drive fixes in pre-silicon environments. Maintain and enhance emulation infrastructure and workflows. PREFERRED EXPERIENCE: Strong experience in SystemVerilog, UVM, and emulation platforms. Proficiency in debugging tools and scripting languages like Python, Perl, or TCL. Familiarity with RTL design (Verilog/VHDL) and simulation tools. Solid understanding of SoC architecture, memory protocols, and interface standards. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #L1-RG2 #hybrid Benefits offered are described: AMD benefits at a glance .

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

About Marvell . Your Team, Your Impact Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives What Were Looking For Bachelor s degree in CS/EE with 8-12 years of relevant experience, or Master s degree in CS/EE with 8-10 years of relevant experience Strong background in IP, Subsystem and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: SoC RTL Integration Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Primary Responsibilities:- Lead complex SoC integration efforts, including the development of top-level architecture and interconnect fabric Design and implement critical integration components such as clock/power distribution networks, reset controllers, and system-level arbitration Resolve sophisticated interface compatibility issues between IP blocks from various sources Develop and maintain comprehensive integration verification strategies Collaborate with IP teams to ensure seamless integration of all subsystems Perform thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis Drive timing closure at the integration level in coordination with physical design teams Implement and optimize system-level power management schemes Lead design reviews and provide technical guidance to junior integration engineers Develop technical specifications for SoC-level integration requirements Required Technical Skills:- 7+ years of RTL design experience with 4+ years focused on SoC integration Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) Proven experience with large-scale integration challenges in complex SoCs Strong understanding of clock synchronization strategies and metastability management Deep knowledge of power management techniques and implementation Experience with integration-specific verification methodologies Proficiency in debugging complex system-level issues Advanced understanding of timing analysis and constraints at the integration level Advanced Capabilities: Ability to identify and address system-level bottlenecks affecting performance Experience optimizing interconnect architectures for bandwidth and latency requirements Knowledge of security isolation requirements for modern SoCs Skill in balancing conflicting requirements from multiple IP teams Experience mentoring junior engineers on integration methodologies Ability to influence architectural decisions based on integration considerations At the MTS level, you would be expected to independently lead major integration efforts, serve as a technical authority on integration challenges, and contribute to architectural decisions that affect the entire SoC design. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Lattice Semiconductor is seeking a Senior Engineer- FPGA Architecture to join the Architecture team focused on FPGA architecture modeling and advance system architecture. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role Specifics This is a full-time individual contributor position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog. The qualified candidate will be working in architecture modeling and evaluation of Lattice FPGA’s and Software tools to measure performance, power, and area for various workloads The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with Software tools team to define benchmarks, measure performance and suggest improvement areas Serve as a technical expert, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and open-minded student Accountabilities Serve as a key contributor to build FPGA architecture modeling and evaluation platform efforts Drive logic design of key FPGA workloads and bring best-in-class methodologies to accelerate design and test time and quality. Develop the regression testing framework to execute, measure and report architecture modeling and evaluation experiments Ensuring design quality throughout project development conducting regular reviews and audits Perform architecture evaluation of competitive products Work with cross functional team including program management, Software Tools, HW architects, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up to date with the latest industry trends and technologies Mentor and develop strong partners and colleagues Occasional travel as needed. Required Skills BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 6+ years of experience in driving logic design across a multitude of FPGA projects. Expertise in FPGA designs, use-cases, and design considerations, defining micro-architecture and experience of working with various EDA tools Experience in leading the project throughout design cycle and working with cross organization Proven ability to work with multiple groups across different sites and time zones. Independent worker and leader with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones.

Product validation and Customer support for High Level Synthesis & Verification Siemens EDA is a leader in automation software for electrical and electronic industries. We enable companies to develop better products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex world of electrical, PCB, and chip design. About the Group: Calypto System Design's Central Engineering Group (CEG) works on pioneering tools like Catapult for High-Level Synthesis, CCOV and SLEC systems for High-Level Verification, and PowerPro for power analysis and optimization. The Product Validation and Customer Support team ensures quality products and satisfied customers in the High-Level Synthesis market. We are a team driven by energy, commonality, and passion. Why Join Us? Do you like to challenge yourself and find innovative solutions to problems, translating them into efficient code? Do you always enjoy learning new things? Are you ready to work on the next-generation synthesis solution technology? If the answer is yes, then come work with us! We don’t need superheroes, just super minds. Role: As an integral part of the Product Validation and Customer Support team, you will test and validate different features of Catapult, CCOV, and SLEC systems, including writing testing specifications and supporting test cases. You will provide solutions and answers to end-users' or field AEs' queries on product usage and identify gaps in the product. You will also maintain the test environment and regression, crafting automated scripts to ensure smooth functioning. Key Responsibilities: Lead projects related to different features of the HLS/HLV product, develop test plans, create test cases, and identify issues and gaps. As the internal end-user of the tool, take measures to improve the quality of the product and test environment. Use technical expertise to respond to customer queries, demonstrate products and their flow, and analyze all incoming issues and queries from customers to identify gaps and improve the product. This role may involve interaction with customers on critical issues to narrow down problems. Support and debug customer design methodologies using our products, produce benchmark data if needed, and participate in architecture reviews and feature prototyping. Understand the tool and user expectations to bring out the best in the tool. Technical Skills (Must Have): B.Tech (EE/ECE/CS) or M.Tech (VLSI/Microelectronics/Embedded Systems) Proficiency in C/C++ for HLS is required. System C is a plus. Experience in running, debugging, validating, and profiling programs on HW design (digital domain) is a huge advantage. Basic knowledge of Verilog/VHDL and experience in Logic Synthesis/High-Level Synthesis is a plus. Knowledge of one of the scripting languages like Perl, Tcl, and experience with LINUX platforms. Excellent problem-solving and analytical skills. Self-motivated and ambitious thinker. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Accelerate transformation

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: 7+yrs of proficient experience in SoC and IP level RTL verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Knowldgeable on AMBA protocols like APB/AHB/AXI etc Required protocols knowledge like USB, I3C, UFS, QSPI etc Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to ARM & RISCV architecture. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SG Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

RTL Design Lead - Memory technologies Hyderabad, India Engineering 64525 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 8+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NR1 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 13+ years of relevant experience Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges Circuit timing/STA, and practical experience with tools Working knowledge of C; embedded experience a plus Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards Been exposed to memory controller and PHYs from different IP vendors Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software Version control systems such as Perforce, ICManage or Git Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.