"> Search Jobs Find Jobs For Where Search Jobs Lead R&D Software Engineer - VC Spy Glass Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 10120 Date posted 03/21/2025 Share this job Email LinkedIn X Facebook Job description (VC Spyglass Lint Technology on VC Platform) Responsible for designing, developing, troubleshooting the core VC-Static engine, which is integral part of Lint Design and develop Lint standard and customized Lint checks using VC Platform technologies for analysis, synthesis and simulations. Will be working closely with other teams both locally and globally Design and development of state of the art EDA tools involving development in one or more of the following areas-: developing new and innovative algorithms in the area of electronic design automation. Skills Required 4 to 10 years of Software development experience Familiarity with ASIC design flow and the EDA tools and methodologies used therein. Fluent in C++ with work experience in data-structures and algorithms. Excellent algorithm analysis skills and a good knowledge of data structures. Good knowledge of Tcl and Perl-based development on Unix. Good knowledge of Verilog, SystemVerilog & VHDL HDL. Ability to develop new architecture Knowledge on GenAI is Value added Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success Quality focus - one who believes in quality and wants to make a difference Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683 Aschheim, Germany Engineering Principal Analog Design Engineer Mississauga, Canada Engineering Verdi Internship Hsinchu, Taiwan Interns/Temp

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Design, Sr Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10299 Date Posted 17/04/2025 You Are: You are a seasoned digital verification engineer with a passion for innovation and problem-solving. With a BE/B.Tech degree in electronics or a related engineering field, you bring 3-5 years of hands-on experience in digital verification. Your proficiency in system verilog, UVM, coupled with a strong understanding of formal verification techniques, sets you apart. You thrive in UNIX/Linux OS environment and have a keen interest in exploring new technologies. Your ability to build UVM based testbenches , along with your prior knowledge of EDA tools and simulators, makes you an ideal candidate. Excellent English communication skills and the ability to compile verification plans and strategies are essential for this role. What You ll Be Doing: Creation of test plans Development of testbenches Creation of tests - both directed and random Functional coverage modelling and review, Code coverage review Debugging and resolving mismatches between design and C-model Integration of third party and internal verification IP Review and improvement of verification test suites and testbench Mentor junior team members Creation of Test plan, test strategy Coverage databases (Fully traceable from test plan and specification) The Impact You Will Have: Driving innovation in processor verification techniques Enhancing the efficiency and effectiveness of our verification mechanisms Contributing to the development of cutting-edge technology that sets Synopsys apart in the industry Ensuring high-quality IP delivery through rigorous verification Supporting the continuous improvement of our hardware verification processes What You ll Need: Bachelor s degree in engineering from a reputed college Minimum 3+ years of relevant experience Microprocessor verification experience is an advantage Hands-on experience with SystemVerilog and Verilog Proficiency with Verification methodologies: UVM/OVM Programming skills: C, assembly, Perl, makefile generation Experience with latest verification techniques like formal, low-power, safety etc. is an added advantage Who You Are: Innovative thinker with a passion for technology Excellent communicator and collaborator Detail-oriented and highly organized Adept at problem-solving and critical thinking Proactive and self-motivated The Team You ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing and verifying ARC processor IPs. Our team values collaboration, creativity, and continuous improvement, and we are dedicated to pushing the boundaries of technology to deliver exceptional products. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

* Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) * Generate verification test plan, verification environment documentation and test environment usage documentation * Define, develop, and verify complex UVM verification environments * Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) * Collaborate with architect, designers , VIP team to accomplish tasks. * Identify design problems, possible corrective actions and/or inconsistencies on documented functionality * Work with peers to improve methodologies and improve execution efficiency. * Adhere to quality standards and good test and verification practices. * Work as a lead, mentor junior engineers, and help them in debugging complex problems. * Able to Support Customer issues, by their reproduction and analysis. * Should be able multitask between different activities. Key Qualifications * Proven desire to learn and explore new state of the art technologies * Demonstrate good written and spoken English communication skills * Demonstrate good review and problem-solving skills * Knowledgeable with Verilog, VHDL and/or SystemVerilog * Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus * Understanding of verification methodology such as UVM . * Good organization and communication skills * Be a solution provider. * 8+ years of relevant experience

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You ll Need: Bachelor s degree in electronics engineering or computer science; Master s degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable. Who You Are: A detail-oriented professional with strong analytical skills. An excellent communicator with the ability to convey complex technical concepts effectively. A team player who thrives in a collaborative, international environment. A proactive learner who stays updated with the latest industry trends and technologies. A problem solver who enjoys tackling challenging technical issues

Designing and verifying digital and mixed-signal circuits for NRZ and PAM-based SerDes products. Collaborating with a team of experienced engineers to deliver high-performance mixed-signal designs. Developing and executing structured firmware development, verification, and documentation processes. Performing functional and performance tests on prototype test-chips. Communicating effectively with different design groups and customer support teams. Balancing good design quality while meeting tight deadlines. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that drive the innovations of tomorrow. Ensuring high-performance and reliable mixed-signal designs that meet unique performance, power, and size requirements. Accelerating the integration of more capabilities into an SoC, helping customers bring differentiated products to market quickly with reduced risk. Enhancing Synopsys reputation as a leader in chip design and software security. Driving the success of our Silicon IP business by delivering high-quality mixed-signal designs. Playing a key role in the continuous technological innovation at Synopsys. What You ll Need: BSEE or MSEE plus a minimum of 5 years industry experience in Silicon Bring up and Functional Validation. Experience with structured firmware development, verification, and documentation processes. Proficiency in digital logic design, simulation, and debug using Verilog and VCS. Demonstrated experience executing projects from start to completion. Good communication skills for interacting between different design groups and customer support teams

Working closely with a world-class R&D team, you ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus - educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment

Designing, developing, troubleshooting, debugging, and maintaining large and efficient software systems for technology mapping, logic, and timing optimization steps of the FPGA logic synthesis software. Gathering requirements and functional specifications, and designing and implementing efficient data structures and algorithms in C/C++. Collaborating with the CAE team in test planning, execution, and customer support. Maintaining and supporting existing products and features. Ensuring that the software meets performance, scalability, and reliability requirements. Staying current with the latest advancements in FPGA design tools and methodologies. The Impact You Will Have: Contributing to the development of industry-leading FPGA logic synthesis software used globally. Enhancing the performance, efficiency, and reliability of FPGA design tools. Driving innovation in the implementation of FPGA designs, prototyping, and debugging of ASICs using FPGAs. Supporting the creation of high-performance, cost-effective FPGA designs through advanced optimization techniques. Collaborating with cross-functional teams to deliver high-quality software solutions that meet customer needs. Helping Synopsys maintain its leadership position in chip design and verification technology. What You ll Need: B.Tech/M. Tech in Computer Science or Electrical Engineering from a reputed institute. 1+ years of experience in designing, developing, and maintaining large EDA software. Strong knowledge of data structures, graph algorithms, and C/C++ programming on Windows/Unix platforms. Familiarity with digital logic design, Verilog/VHDL RTL level designs, timing constraints, and static timing analysis. Working knowledge of FPGA design tools and flows is a plus. Who You Are: Proactive and detail-oriented with a strong commitment to quality and excellence. Exceptional problem-solving skills and the ability to tackle complex challenges creatively. Collaborative team player with excellent communication and interpersonal skills. Passionate about continuous learning and staying current with technological advancements. Adaptive and flexible, thriving in a dynamic and fast-paced work environment

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.

At minimum, a Bachelor s degree in engineering is required with 12+ years of digital design experience using Verilog. Strong background in RISC architectures required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful. The successful candidate is expected to: Design embedded RISC microprocessor IP at architectural and RTL level Write High-level architecture and micro-architecture specifications of the design Optimize design for performance, speed, area and power, generate hardware benchmarks and analyze results Develop standalone Verilog testbenches to verify their module Debug design issues / bugs working closely with the verification team Maintain our current processor product line and their derivative products Develop and maintain project plans. Work closely with program managers Good written, oral and problem-solving skills desired along with good communication skills and inter-person skills Work with multi-site, multi-time zone, multi-cultural teams on various aspects of the product like design, implementation, physical design, verification

As an ideal candidate, you are a passionate and highly skilled engineer with a keen interest in ASIC physical design. You possess a strong foundation in electronics engineering or computer science, ideally with a Bachelors degree and a minimum of 3 years of related experience. You have a methodical approach to problem-solving and are proficient in scripting languages like Unix, Perl, and TCL. Your exposure to Verilog/VHDL and understanding of microprocessor design make you a valuable asset to any team. You are a team player with excellent written and verbal communication skills, capable of working in a collaborative international environment. Your enthusiasm for learning and applying new technologies drives you to continuously improve and contribute to cutting-edge projects. What You ll Be Doing: Contributing to the physical design and implementation of our highly optimized hardware IP for the ARC family of configurable processors. Working on the full SOC design cycle with a focus on physical design tasks, including floorplanning, placement, routing, and timing closure. Collaborating with cross-functional teams to ensure the successful integration and verification of our microprocessor IP. Assisting in customer sales and design-ins of our IP by providing technical support and expertise. Participating in in-house test chip designs and development platforms to explore potential applications of our microprocessor IP. Engaging in benchmarking and qualification activities to ensure the highest performance and reliability of our products. The Impact You Will Have: Enhancing the performance and efficiency of our microprocessor IP through innovative physical design techniques. Contributing to the development of state-of-the-art embedded designs used in various high-tech applications. Supporting the successful deployment of our IP in customer projects, leading to high customer satisfaction and repeat business. Driving continuous improvement in our implementation flows and methodologies. Helping Synopsys maintain its leadership position in the semiconductor industry by delivering top-quality products. Fostering a collaborative and innovative work environment by sharing your expertise and learning from others. What You ll Need: Bachelor s degree in electronics engineering or computer science; a Master s degree is a plus. Minimum of 3 years of related experience in ASIC physical design. Proficiency in Unix, Perl, and TCL scripting. Exposure to Verilog/VHDL and understanding of microprocessor design. Strong written, verbal, and methodical skills. Who You Are: A collaborative team player with excellent communication skills. A methodical problem-solver with a keen attention to detail. Enthusiastic about learning and applying new technologies. Adaptable and able to work in an international, multi-disciplinary team. Dedicated to continuous improvement and innovation.

As an ideal candidate, you are a seasoned professional with a passion for innovation and a deep understanding of ASIC design and verification. You have a proven track record in developing high-level verification environments using System Verilog/UVM and possess a keen eye for detail. Your expertise in memory interface protocols like DDR and LPDDR sets you apart, and you excel in debugging and problem-solving skills. You are self-motivated and possess excellent communication skills, enabling you to work seamlessly within global teams. Your leadership abilities allow you to guide technical teams and enhance verification strategies and test environments, ensuring high-quality deliverables. What You ll Be Doing: Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Manage and own a team to develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enable the creation of high-performance silicon chips and software content, driving innovation in various industries. Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning. Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security. What You ll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 10+ years of relevant experience. Proven experience in developing HVL (System Verilog/UVM) based test environments. Expertise in developing and implementing test plans, checkers, and assertions. Proficiency in extracting verification metrics such as functional coverage and code coverage. Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes

As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction. We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead: As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy - verification is the key to avoid white spots mixing with stars. We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks. Job role and Skill set - Design role: Senior RTL Subsystems Designer Lead role. With 8+ years of experience. Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s). Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Hands-on experience with low power design. Understanding of DFT requirements and architecture. Working with cross-functional teams and driving the projects to completion. Job role and Skill set - Verification role: Senior Verification lead role. With 8+ years of experience. Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage. Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add. Working with cross-functional teams and driving the projects to completion.

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols such as Ethernet, DDR, and PCIe Your technical expertise is complemented by your hands-on experience in simulation, synthesis, and static timing analysis (STA) With a Bachelors and/or Masters Degree in Electrical Engineering or a related field, you bring at least 10 years of design, verification, or application engineering experience to the table You thrive in a UNIX environment and are proficient with ASIC/SoC tape-out processes from concept to full production Your ability to work across teams, coupled with strong analytical, reasoning, and problem-solving skills, sets you apart as a creative and results-oriented professional Excellent verbal and written communication skills in English are essential, as you will be collaborating with customers and teams worldwide Occasional travel is something you are comfortable with, and you are ready to take on the challenge of integrating leading Interface IP into next-generation products What You ll Be Doing: Acting as a trusted advisor for our Interface IP customers, providing guidance throughout their SoC flow. Supporting customers in resolving technical challenges and performing integration reviews at key milestones. Assisting with silicon/system bring-up and debugging critical issues. Collaborating with internal teams to deliver tailored solutions to customers. Staying updated with the latest industry specifications and applications in various hot market segments. Participating in occasional travel to support customer engagements and silicon bring-up activities. The Impact You Will Have: Enhancing the usability and adoption of Synopsys Interface IP products by providing expert technical support. Facilitating successful integration of IP into customer designs, contributing to their product development timelines. Improving customer satisfaction by resolving technical issues efficiently and effectively. Driving innovation by working with cutting-edge technologies and industry specifications. Strengthening Synopsys market position through successful customer engagements and support. Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP. What You ll Need: Bachelors and/or Masters Degree in Electrical Engineering or similar with a focus on VLSI design. At least 10 years of design, verification, or application engineering experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet, DDR, and PCIe. Hands-on experience with simulation, synthesis, and static timing analysis (STA). Familiarity with UNIX environments and ASIC/SoC tape-out processes. Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus. Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements.

We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys position as a leader in the semiconductor industry through successful project deliveries. What You ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement

Reviewing SerDes standards to develop analog sub-block specifications. Identifying and refining circuit architectures to achieve optimal power, area, and performance targets. Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design. Overseeing physical layout to minimize the effects of parasitics, device stress, and process variation. Presenting simulation data for peer and customer review. Documenting design features and test plans. Consulting on the electrical characterization of your circuit within the SerDes IP product and proposing solutions for post-silicon design updates. The Impact You Will Have: Contributing to the development of high-performance SerDes IP that meets industry standards. Optimizing power, area, and performance of analog circuits, driving efficiency and innovation. Ensuring high-quality designs through meticulous verification strategies and simulator features. Improving the reliability and robustness of integrated circuits through careful layout oversight. Enhancing customer satisfaction by presenting comprehensive simulation data and supporting design reviews. Facilitating post-silicon design updates with your expertise in electrical characterization. What You ll Need: BE+6 years of relevant experience or MTech+4 years of relevant experience in Electrical Engineering, Computer Engineering, or a related field. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one SerDes sub-circuit and familiarity with several others (e.g., receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC). Aware of ESD issues and circuit techniques. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability (EM, IR, aging, etc.). Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Knowledge of SPICE simulators and simulation methods. Proficiency in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB. Who You Are: A highly analytical thinker with a strong attention to detail. A collaborative team player who thrives in a diverse work environment. Excellent communicator with strong documentation skills. A proactive problem-solver who can identify and implement solutions effectively. Adaptable and open to learning new technologies and approaches

You are a highly skilled and experienced Analog Design Engineer with a passion for developing cutting-edge technology. With a strong foundation in Electrical or Computer Engineering, you have honed your expertise in transistor-level circuit design and are adept at working with high-speed analog integrated circuits. Your deep understanding of CMOS design fundamentals and familiarity with various SerDes sub-circuits make you an invaluable asset to any team. You thrive in collaborative environments, working seamlessly with cross-functional teams of analog and digital designers. Your meticulous approach ensures optimal power, area, and performance targets are met, and your innovative design strategies push the boundaries of what is possible. You are not only technically proficient but also possess excellent communication and documentation skills, allowing you to effectively share your ideas and results with peers and customers. Your proactive attitude and problem-solving abilities make you a go-to person for post-silicon design updates and electrical characterization. In summary, you are a seasoned professional ready to take on the challenges of high-speed analog integrated circuit design in the latest FinFET process nodes. What You ll Be Doing: Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need: BE with 5+ years of relevant experience or MTech with 4+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are: Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive and detail-oriented leader who can guide and mentor a team. An excellent communicator who can collaborate effectively with cross-functional teams. A problem-solver who can anticipate challenges and develop effective mitigation strategies. A continuous learner who stays updated with the latest verification tools and methodologies. A team player who values quality and strives for excellence in deliverables

Characterizing and modeling standard cells for various technologies and foundries. Conducting quality analysis of characterized liberty and Verilog models in terms of timing, power, and functionality. Validating characterization and simulation tool versions including PrimeLib, Hspice, PrimeSim, and Finesim. Providing daily status updates on project progress. Ensuring timely and quality releases of projects. Collaborating with cross-functional teams to enhance design and verification processes. The Impact You Will Have: Enhancing the accuracy and efficiency of standard cell models across various technologies. Improving the quality and reliability of characterized models in terms of timing, power, and functionality. Streamlining validation processes for characterization and simulation tools, ensuring robust tool versions. Contributing to the timely delivery of high-quality releases, meeting project deadlines and standards. Supporting technological innovation through meticulous analysis and validation. Fostering collaboration and knowledge sharing within cross-functional teams for continuous improvement. What You ll Need: 5 Years of experience in Standard Cell Characterization Thorough knowledge of MOSFET and FINFET technologies. Experience with PrimeLib, Hspice, PrimeSim, and Finesim tools. Strong analytical skills for quality analysis of characterized models. Proficiency in characterizing and modeling standard cells for various technologies. Excellent communication skills for providing daily status updates and collaborating with teams. Who You Are: A detail-oriented professional with a strong analytical mindset. A proactive communicator, able to provide clear and concise updates. A collaborative team player, ready to work with cross-functional teams. A dedicated individual committed to delivering high-quality work on time. An innovative thinker, always looking for ways to improve processes and outcomes.

Develop and maintain automation scripts for CAD tools using languages like Python, Perl, or TCL. Collaborate with designers and engineers to identify automation opportunities and implement solutions. Design and implement automation frameworks for design flow of multiple functions using AI. Proficient in troubleshooting and debug automation scripts and CAD tool issues. Develop and maintain documentation for automation scripts and processes. Understanding of DV flow and generating test benches and test cases. Understanding RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Understanding CAD infrastructure, methodology will help to setup project environment. Contribute to enhance quality assurance methodology by adding more quality checks/gatings. Front End development process understanding and support Internal tools development and automation to help improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understanding of tools like VC Spyglass, Verdi, & views like SDF, Liberty etc and other frontend views will add value to this position. Writing RTL Code, Solid Verilog, PERL, and Python skills and TCL are good additions. Understanding static timing analysis and synthesis, DFT/ATPG skills would be a plus. Previous knowledge of customer support and/or silicon bring-up is a plus. Drive automation to enhance IP Quality-Assurance flow & Release process. Define and establish a comprehensive QA process for IP development. Integrate new features and functionalities into IPQA scripts with automation team. Streamline the release process to reduce cycle time and improve efficiency. Automate release tasks, such as packaging and documentation, to reduce manual errors. Improve release quality by integrating QA processes into the release workflow. Enhance releasing documentation to ensure completeness and accuracy. Validate the integrity of the release package by checking for corruption, tampering, or other issues (Time Stamp and Locking Source of Release package and Release package itself). Required Skills: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Excellent problem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering OR M.E/M.Tech in VLSI Design/Microelectronics with 8-15 years of relevant experience. * Hands-on experience in architecting and building System Verilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience with Display Port/HDMI/MIPI/USB/PCI-E protocol preferably the latest specifications * Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills.

We are seeking a Senior FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, you'll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as we'll as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (eg, Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A masters degree in Electrical or Computer Engineering or equivalent