2321 Verilog Jobs - Page 41

Qualification: BTech / MTech in Signal Processing / Communication Systems Job Profile Required to work on development and implementation of signal processing algorithms, firmware development for various interfaces in Radar. Should have hands-on experience in handling the Embedded Hardware and Firmware designs. Responsibilities : Algorithm development, simulation & implementation using Vivado / Matlab / Python. Radar Subsystem integration & testing. Embedded Hardware & Firmware development using FPGA / DSP / Microcontroller. High-speed ADC, DAC, DDR, Ethernet and other peripheral interface designs with FPGA. Hands-on experience on FPGA design tools (Vivado, Vitis HLS, System Generator) and PCB/Schematic design tools (Cadence, Allegro PCB Editor). Knowledge of various communication protocols (Ethernet, Serial, CAN, VME, VPX etc) Experience & Skills require d : 6+ years of experience in firmware design / FPGA / DSP, with a focus on radar applications Programming languages: Maltab, VHDL / Verilog, C Programming Radar Signal Processing, Matlab, Hands-on experience on Vivado FPGA tools. Experience on RF-ADC/DAC, RFSoC interfaces, Python are desirable

Experience in dft scan insertion, atpg at ip and soc level Hands on experience in atpg timing and no-timing simulations Proficient in doing basic unit-level verification using simulations. Scan/atpg patterns & test flows development, debug, test and characterization

We are looking for a control firmware engineer with 8+ years of experience in embedded communication firmware development with expertise in Description Understand product requirements / Firmware specifications / communications firmware architecture for Solar Energy Grid Tie / Off Grid Inverters /Back-up systems / Auxiliary Products like communication Gateways and Operator/service Interfaces applications. Hands on Code Implementation / debugging / development and testing of systems Development of real time state machine, monitoring and communications functions for the above referred renewable energy products. Understand and comply with QMS, PMP and lean development requirements Participate in subsystem and system level design verification planning and testing Essential Functions: Programming language C/C++ for 32 bit microcontrollers, RTOS environments like uC OS-II/QNX/embedded Linux or other platforms. Experience in Bootloader development and reliable firmware upgrade mechanisms. Familiarity with embedded testing ,test automation scripting for embedded products, development tools, including emulators and version control software. Exposure to advanced real time firmware debugging tools like J-Trace, logic analyzers, time/performance profiling techniques etc.. Experience Cyber security complained firmware development, System level/sub system level Threat modeling, good understanding on TCP/IP based communication stacks, various encryption techniques, Authentication/ authorization algorithms/models. Scripting languages like Python and Lua. Experience in industrial field bus communication protocols like MODBUS / CAN and protocols like USB, TCP/IP and embedded webservers. Exposure in WIFI/Bluetooth based communication interface development. Exposure to Web technologies like HTML, JavaScript is preferred. Good interpersonal communication skills and experience in working with global teams Qualifications

Experienced in rtl design using verilog / system Verilog Asic designers with experiences in all aspects of rtl design flow from specification/microarchitecture definition to design and verification, timing analysis, dft and implementation Integration, rtl signoff tools, upf/low power signoff and cdc/rdc, lint Strong domain knowledge of clocking, system modes. Power management, debug, interconnect, safety, security and other architectures

Experience in Static Timing Analysis (STA) for ASIC designs Experience in developing timing constraints Experience in timing closure and optimization Proficiency in using scripting languages such as Perl and TCL Familiarity with EDA tools such as PrimeTime and Design Compiler Experience in Physical Design and/or DFT is a plus Bachelor s or Master s degree in Electrical/Electronics/Computer Science Engineering or related field

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. BTech/ MTech in Engineering with 15 to 18 years of actual work experience in Hardware Design Architect.Worked on PCIE/LPDDR5/UCIE/Ethernet/MIPI Protocol Designs. Prepare SOC hardwareArchitecture Specification to Start the Design and Verification Implementation. Verilog / System-Verilog RTL logic design, debug, and functional verification supportN/A We’re doing work that matters. Help us solve what others can’t.

NVIDIA data center systems, such as DGX and HGX, have become core to NVIDIA's rapidly growing enterprise and cloud provider businesses. These platforms bring together the full power of NVIDIA GPUs, NVIDIA NVLink, NVIDIA InfiniBand networking, NVIDIA Grace CPUs, and a fully optimized NVIDIA AI and HPC software stack. We are hiring Sr. Software Engineer who will help build simulators for our DGX Server platforms. Simulations play a significant role in building scalable systems at Speed of Light! You will work with world class engineering teams across HW and SW. What You’ll Be Doing Contribute to architect and develop simulation platform for next-gen NVIDIA Data Center platforms. Build, integrate and enhance simulator components with new HW features and write supporting technical documents. Bring full SW stack up on Data Center Platform Simulator; work closely with hardware modeling, kernel & platform driver teams distributed globally. Improve performance, fix bugs across user and kernel stack, and automate execution flow. What We Need To See Proficient in C/C++ with strong software development, optimization, user & kernel mode debugging skills. OS fundamentals and system architecture understanding like low-level interfaces such as buses, controllers, interrupts etc. Good understanding of hypervisors & HW emulators, like QEMU, KVM, VDK, Simics, etc. Working experience on any one major Linux distro like Ubuntu, RedHat, SLES etc. Strong interpersonal & communication skills to work with a globally distributed engineering team. Bachelor’s degree in computer science or related (or equivalent experience) with 5+ years of relevant experience. Ways To Stand Out From The Crowd Experience in HW & SW stack bring up using Simulators & Emulators etc. Previous experience around hardware interfaces such as PCIe, SPI, I3C etc with Linux boot solutions on x86 & ARM class platforms. Experience in Out of Band and Inband management architectures. Contribution in QEMU/KVM opensource repositories. Experience in Verilog and SystemC. We have some of the most forward-thinking and hardworking people on the planet working for us. If you're creative, passionate, and self-motivated, we want to hear from you! JR1997525

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at SOC level. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronic with 2+ year experience in verification domain. Prior work experience on IP level or Soc level. Good understanding of process Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Assistant Manager / Manager – Radar Sign... LNT/AM-M-RSP/1381601 DEIC-L&T Precision Engineering & Systems ICBengaluru Posted On 27 Jun 2025 End Date 24 Dec 2025 Required Experience 6 - 9 Years Skills Knowledge & Posting Location DIGITAL SIGNAL PROCESSING MATLAB SIMULINK EMBEDDED C FPGA DESIGN Minimum Qualification BACHELOR OF TECHNOLOGY (BTECH) MASTER OF TECHNOLOGY (MTECH) Job Description Qualification: BTech / MTech in Signal Processing / Communication Systems Job Profile Required to work on development and implementation of signal processing algorithms, firmware development for various interfaces in Radar. Should have hands-on experience in handling the Embedded Hardware and Firmware designs. Responsibilities : Algorithm development, simulation & implementation using Vivado / Matlab / Python. Radar Subsystem integration & testing. Embedded Hardware & Firmware development using FPGA / DSP / Microcontroller. High-speed ADC, DAC, DDR, Ethernet and other peripheral interface designs with FPGA. Hands-on experience on FPGA design tools (Vivado, Vitis HLS, System Generator) and PCB/Schematic design tools (Cadence, Allegro PCB Editor). Knowledge of various communication protocols (Ethernet, Serial, CAN, VME, VPX etc.) Experience & Skills require d: 6+ years of experience in firmware design / FPGA / DSP, with a focus on radar applications Programming languages: Maltab, VHDL / Verilog, C Programming Radar Signal Processing, Matlab, Hands-on experience on Vivado FPGA tools. Experience on RF-ADC/DAC, RFSoC interfaces, Python are desirable

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: MTS SILICON DESIGN ENGINEER THE TEAM: AMD's NTSG - Network Technologies Solutions Group is a leading provider of data center networking technology. The distributed services platform will expand AMD's data center product portfolio with a high-performance data processing unit (DPU) and software stack that are already deployed at scale across cloud and enterprise customers including Goldman Sachs, IBM Cloud, Microsoft Azure and Oracle. THE PERSON: We are hiring a ASIC Verification Engineer to help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain specific processors for the IAAS and smart-switch markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and security virtualization services for both the public and private cloud markets. THE ROLE: In this role, you will be responsible for defining test strategies and plans, developing test benches and test cases, and debugging designs helping with micro-architecture. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. Your work and skills will be leveraged across module-level, full chip, emulation, prototyping, silicon bring-up, manufacturing diagnostics, compilers, and shipping platform software. KEY RESPONSIBILITIES: With your solid knowledge and understanding of Computer Architecture you will be: Developing and executing test plans for Unit/IP/Subsystem/ SOC level verification System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills PREFERRED EXPERIENCE: Languages and tools: UVM, System Verilog, C or C++ System Verilog simulators and waveform debuggers Experience developing and executing test plans for Unit/IP/Subsystem/ SOC level verification Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) Solid knowledge and understanding of Computer Architecture Excellent debugging and problem-solving skills ACADEMIC CREDENTIALS: BSEE or equivalent. MSEE preferred Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling. Work closely with design/verification teams within CPU to develop comprehensive test plan. Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus. Verify power intent through use of methodologies like UPF. Work closely with system architects, software teams and Soc team to validate system use cases. Work closely with emulation team to enable verification on emulators and FPGA platforms. Debug and triage failures in simulation, emulation and/or Silicon. BE/BTech degree in CS/EE with 3+ years’ experience. Experience in power management verification. Implementation of assembly and C language embedded firmware. Experience in C/C++, scripting languages, Verilog/system Verilog. Strong understanding of power management features in CPUs and CPU based Socs. Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc. Preferred Requirements Good Understanding of CPU architectures and CPU micro-architectures. In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture Experience with advanced verification techniques such as formal and assertions is a plus Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071121

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a passion for innovation and a drive for excellence. You possess a strong background in digital design and verification, with a keen understanding of microprocessor architectures. Your technical expertise and analytical skills enable you to develop and maintain complex hardware-software co-simulation environments, create functional and code coverage models, and manage regression testing effectively. You thrive in a collaborative, multi-cultural, and multi-time zone team environment, and your excellent communication skills allow you to work seamlessly with colleagues and stakeholders. Your experience with HDL and verification languages such as System Verilog and Verilog, along with your proficiency in programming languages like C, C++, assembly, Python, and Perl, make you an invaluable asset to the team. You are adept at using RTL simulators and other verification tools, and you are always eager to learn and adapt to new technologies and methodologies. What You’ll Be Doing: The candidate will be a key member of the Synopsys DesignWare ARC Processor hardware team working on next-generation ARC processor Verification. Responsibility includes development of Processor Testbenches and automation, functional coverage model creation and report analysis, code coverage analysis, integration of third party and internal verification IP, regression management. Candidate is expected to work with multi-site, multi-time zone, multi-cultural teams on various aspects ARC processor verification. Creating and automating testbenches for verification processes. Creating functional coverage models and analyzing reports. Performing code coverage analysis to ensure thorough verification. Integrating third-party and internal verification IPs. Managing regression testing and ensuring test coverage. The Impact You Will Have: Ensuring the reliability and performance of next-generation ARC-V processors. Contributing to the development of cutting-edge silicon IP solutions. Enhancing the efficiency and effectiveness of verification processes. Reducing time-to-market for high-performance, low-risk products. Collaborating with global teams to drive innovation and excellence. Helping Synopsys maintain its leadership in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering (required). 4+ years of related experience in digital design and verification. Strong knowledge of digital design principles. Experience with microprocessor architectures (a plus). Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Experience with RTL simulators and verification tools. Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural environment. Analytically minded with exceptional problem-solving skills. Detail-oriented and committed to delivering high-quality work. Adaptable and eager to learn new technologies and methodologies. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Become a Pioneer in Computing - Join Vicharak! At Vicharak , we stand at the vanguard of a computing revolution. Similar to the trailblazers at Bell Labs in 1947 who witnessed the birth of the transistor, we're revolutionizing the future of semiconductors through innovative FPGA technology. Unlike traditional processors, our FPGAs enable programmable changes in inner circuitry, unlocking new dimensions in parallelism, speed, and computing. Our groundbreaking VAAMAN hardware system, combining FPGA and SBC, epitomizes our innovation, and we're searching for talented individuals who share our fervor for this field. We invite researchers, developers, designers, engineers, and architects to join us in crafting the next era of computing. What You'll Learn: Software languages: C/C++, Python, HDL languages like Verilog and System Verilog. Utilize diverse tools, including compilers such as GCC and X86s, alongside IDEs like Visual Studio and PlatformIO. Master FPGA tools like Vivado, Radiant, and Efinix FPGAs. Develop adaptable skills to tackle challenges effectively and gain insights spanning from keyboards to complex servers. What You'll Work On: Engage in our thrilling projects, delving into various facets of our Acceleration framework encompassing AI Acceleration, Software Acceleration, and optimizing peripherals. Gain hands-on experience in Verilog and System Verilog, mastering the fundamentals of these languages. Join Us at Vicharak - Shape the Future of Computing! If you possess an unwavering interest in this field and an insatiable thirst for knowledge, we want to hear from you! Come be part of Vicharak and be at the forefront of molding the future of computing through our groundbreaking FPGA technology. For more insights, visit our website: https://vicharak.in

3+Yrs Exp.Android device platform, Proficient In Kotlin Language knowledge of design patterns like MVP, MMVM, RxJava, and others knowledge of Android SDK, NDK, Android Studio, Gradle, and Lint Knowledge of Flutter or React native will be an advantage Required Candidate profile Candidate will be able to build and integrate android libraries and modules and design-build and maintain high performance reusable java and OOPS concept

We are looking for a Staff Data Scientist to join our Silicon Verification Data Science team. In this role, you will use advanced data science, AI/ML techniques to drive efficiency, automation, and innovation in Silicon Design Verification. You will work closely with hardware engineers, verification teams, and software developers to optimize verification workflows, improve coverage, and accelerate time-to-market for cutting-edge semiconductor products. As a Staff Engineer/ Data Scientist at Micron, you will Develop AI and Data Science based solutions to build state-of-the-art solutions for silicon design verification and firmware validation. Identify patterns, anomalies, and inefficiencies in silicon design verification processes and develop solutions to address these gaps. Automate data pipelines and develop tools to support regression analysis, bug triaging, and root cause analysis. Partner with cross-functional teams to integrate data-driven solutions into EDA tools and verification frameworks. Drive technical innovation and culture within the team by participating in generating IP and inspiring team to innovate. Participate in end-to-end project scoping and stakeholder discussions to determine technical merit of the idea, vale proposition and resource requirements. Interact with subject matter experts to define scope, identify risks, deploy scalable solutions & lead multiple projects execution Continuously learn as we'll as mentor team on recent progress on semiconductor and AI/ML domain. Key requirements: Education: masters or PhD in Computer Science, Electrical Engineering, or a related field. Experience: 8+ years in data science and machine learning with at least 2 years in semiconductor verification environment Technical Skills In-depth understanding of Statistics, classical ML and deep learning, and the mathematics and formulation behind these algorithms. we'll versed with text processing, various methodologies in data embedding, NLP techniques and recent advancements in GenAI and LLMs. Hands-on experience with optimization and reinforcement learning based algorithms. Solid understanding of data engineering pipeline for deployment and MLOps. Proficiency in programming languages such as Python, R, and SQL. Experience with machine learning frameworks (eg, TensorFlow, PyTorch) and data visualization tools (eg, Tableau, Power BI). Strong understanding of digital design and verification concepts (eg, RTL, UVM, coverage metrics, simulation). Experience with EDA tools (eg, Synopsys VCS, Cadence Xcelium, Mentor Questa) and verification flows is a great plus. Preferred Qualifications: Knowledge of hardware description languages (Verilog/SystemVerilog). Experience with CI/CD pipelines and MLOps practices. Patents or publications in relevant fields.

We are looking for marketing Executive activities, Business development person with good communication skills and positive attitude [Need to achieve sales targets] Should be able to understand the customer requirement and fulfill by coordinating with team. Responsible in marketing activities such as Presentations and Seminars Our company. To understand the need of the customer and demonstrate the company products and services to them. Marketing and business development, Team Management Marketing Executive: 1 Good team player who can offer inputs for enhancing business growth and also possess eagerness to learn new things. Desired Candidate Profile Good communication skills Someone hardworking, with a basic idea of marketing, with a positive attitude towards learning more. Good Communication Skill, Hindi ,& English will be preferred.Basic Computer Knowledge. Should be MBA in Marketing Good Communication, Presentable, Active, Self Motivated, Ready to do field work A candidate who is management graduate with marketing specialization, MBA preferable. . Must have good Knowledge of Computers & MS-Office Should be a hard worker having capabilities to achieve target.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: The candidate will be responsible for working in the formal verification domain, specifically targeting designer applications within JasperGold. Additionally, the candidate will contribute to machine learning initiatives into designer apps. Candidate should have 1 -2 years of experience and be proficient in C++ with a strong understanding of data structures and algorithms. Knowledge of Verilog, VHDL and Qt is a plus. We re doing work that matters. Help us solve what others can t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Software Engineer II Location: Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing learning opportunities, and celebrating success in recognition of the specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirements and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary As a software engineer II, you will work on the latest specs to develop, optimize and enhance the VIP codebase for performance, scalability, and reliability, ensuring adherence to industry standards and best practices. You will also collaborate and work closely with architects, verification engineers, and other R&D teams to understand requirements and contribute to the overall development roadmap. In this role, you will be an integral part of developing advanced Verification IP solutions, contributing to the innovation and reliability of our products. This involves working closely with the customers to understand their key challenges, develop efficient methodologies, help them leverage the latest tool capabilities, and guide them to achieve their design goals. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest designs that customers are working on, and influence at all internal and external levels. You will be participating actively in brainstorming sessions, contribute creative ideas, and explore new technologies to improve and expand our VIP offerings. Experience and Technical Skills required 2 to 5 years of experience in verification Expertise in SV, UVM, Verilog Good understanding of functional coverage and Randomization Good understanding of C/C++ languages Knowledge of scripting languages & VIP development is a big plus Must have excellent debugging skills and the ability to separate out the critical issues from trivial ones. Job Responsibilities : Quickly ramp up on new technologies Independently develop the new functionalities/features in C/C++ Develop and execute a verification plan Test plan and test bench development in SV/UVM Functional Coverage creation Debugging complex issues independently Committed to delivering high-quality features in the defined timeline Qualifications: BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We re doing work that matters. Help us solve what others can t.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience 4 years of experience with digital design in ASIC Experience in RTL design utilizing Verilog/System Verilog with ARM-based SoCs, interconnects, and ASIC methodology Experience in a scripting language, such as Python or Perl Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience Experience with AMBA (Advanced Microcontroller Bus Architecture) protocols Experience with methodologies for RTL quality checks (e g , Lint, CDC, RDC) Experience with methodologies for low power estimation, timing closure, synthesis Experience with a scripting language like Python About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Define microarchitecture details including interface protocols, block diagrams and data flow Perform RTL quality checks such as Lint, CDC, and Synthesis checks Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up Collaborate within a team to develop and deliver optimized interconnect blocks and subsystems Coordinate with architecture, design verification, and implementation teams to ensure specification adherence and Communicate and work with multi-disciplinary and multi-site teams Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Minimum qualifications: Bachelor's degree in Computer Science, IT, a related field, or equivalent practical experience 5 years of experience with static timing analysis, synthesis, physical design & automation Experience in physical design tool automation such as synthesis, P&R and sign-off tools Preferred qualifications: Experience in extraction of design parameters, QoR metrics, and analyzing data trends Knowledge of RTL languages (e g , Verilog and SystemVerilog) Knowledge of timing constraints, convergence and sign-off Knowledge of STA, EMIR and PDV sign-off methodologies Understanding of parasitic extraction tools and flow About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Work with Post-Si teams to improve and debug Vmin and yield related issues Explore specific new custom circuit opportunities for optimized Power, Performance, and Area (PPA) for high-performance, low-power subsystems Work with the testchip teams on latest process nodes to build, validate and characterize custom Intellectual Property (IPs) Schedule and plann for custom IP for product interception Work on early prototyping of subsystems to deliver optimized PPA recipes Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) Experience in micro-architecture and design of subsystems Preferred qualifications: Experience in SoC designs and integration flows Experience with scripting languages (e g , Python or Perl) Knowledge of high performance and low power design techniques Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies About The Job In this role, youll work to shape the future of AI/ML hardware acceleration You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems You will be part of a team developing ASICs used to accelerate and improve traffic in data centers You will collaborate with members of architecture, verification, power and performance, physical design, etc to specify and deliver quality designs for next generation data center accelerators You will solve technical problems with innovative micro-architecture and logic solutions, and evaluate design options with complexity, performance, power and area in mind The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc ) and Google Cloud Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing Our global impact spans software and hardware, including Google Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers Responsibilities Own microarchitecture and implementation of subsystems in the data center domain Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications Perform Quality check flows like Lint, CDC, RDC, VCLP Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams Identify and drive power, performance and area improvements for the domains owned Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form

Introduction As a Hardware Engineer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role And Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Preferred Education Master's Degree Required Technical And Professional Expertise 5 + years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in DFT Verification - Demonstrated execution experience of verification of Memory BIST Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good object-oriented programming skills in C/C++, and any of scripting languages like Python/Perl Development experience on Linux/Unix environments and in GIT repositories and basic understanding of Continues Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in verification coverage closure Hardware debug skills backed by relevant experience on projects Preferred Technical And Professional Experience Knowledge of Chip-Initialisation , SCAN , etc Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position presents an opportunity to join the award winning and market leading Tessent team, India. The focus of the role is advanced design-for-test (DFT) insertion and automatic test pattern generation (ATPG) for semiconductor designs. It will involve understanding and supporting the latest DFT ATPG electronic design automation (EDA) technologies such as Tessent TestKompress and Streaming Scan Network (SSN). Someone in this role will gain a deep understanding of scan design, on-chip clock controls, and IJTAG infrastructure in support of scan testing. They will support the worldwide application engineering team on complex ATPG issues and build testcases for advanced DFT methodologies. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. Responsibilities for this role include: Build and deliver in-depth technical presentations, develop training material, white papers, supplied articles, and application notes. Work with customers as well as Siemens stakeholders such as regional application engineers, global support engineers, and marketing. Are you expertized in working through complex technical issues and independently building solutions and new methodologies! Explain complex principles in simple terms to broad audiences. Some travel, domestic and international. Successful deployment of existing and new Tessent DFT products in customer designs by enabling AEs. Working closely with our key customers on deployment challenges. Working with PEs and R&D to ensure new product readiness testcase in form of testcases, documentation and trainings. Architecture reviews of customer designs. Closely working with AEs to gather top issues blocking their engagement's success. Deep learning opportunities for Tessent DFT products including opportunities to present at various conferences worldwide including ITC and Siemens U2U. We dont need hard workers, just superminds! BS degree (or equivalent) in Electrical Engineering, Computer Science or related field is required with 8 - 12 years of experience. Knowledge of design logic design languages, tool usage, design flow steps required. We are looking for someone that has exposure to DFT or SoC design for complex ASICs / SOCs. ATPG, IEEE 1687 IJTAG, boundary scan (BSCAN), hierarchical DFT implementation. Knowledge of a scripting language like TCL. We need someone self-motivated and dedication to improvement with strong problem-solving skills. Excellent organizational skills, written and verbal English language communication skills. Proficiency in LINUX and Windows environments. The role presents many opportunities to build specialized DFT and ATPG knowledge. Publications and other promotions of methodologies is encouraged. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-HYBRID