1574 Verilog Jobs - Page 44

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

About The Role This position is for an experienced, motivated, and passionate circuit design engineer with expertise in the area of custom circuits memories, SSARF SRAM, Register File, ROM design for GHI CCG SAI Circuits Team. In this position you will be working in a team responsible for delivering high quality designs for graphics projects. You would also be involved in key decisions finalizing the memory architecture that best meets the design requirements of the program, technical readiness involving circuit simulations and responsibility for implementation as well as convergence of the design while meeting high circuit quality. The key responsibilities include ownership of tools, flows, methodologies as well as coming up with innovative design implementations with focus on power and area reduction. The role would require deep understanding of transistor and circuit behavior, strong communication, problem solving skills, time management and multitasking skills. The team members have also an opportunity to diversify their skills into other custom circuits as well as working with the client in integration of the custom circuits. Qualifications Minimum QualificationsMinimum 4-7 years of experience in designing and delivering of SRAM's/RF's/ROM's. Understanding of semiconductor device physics; VLSI Technology and VLSI circuits (analog/digital), Familiarity with spice simulations and Verilog and other tools for design and development of memory IP's like ESPCV, Nanotime, Nova, Totem etc. Knowledge of scripting (PERL/TCL/Python) is desirable, Preferred Educational QualificationsME/Mtech/MS in Microelectronics/VLSI Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Job Description InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Senior Engineer - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning! Key Responsibilities You will be working within DV team on verifying ORAN packet processing blocks using internal developed reference Python Model. Work on high speed SERDES interface verification such as PCIE but not limited to. Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate. Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level. Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs. Develop and execute verification plans based on design specifications and collaboration with architects and designers. Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences. Execute and Debug use-cases. Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification. Debug test cases and report verification result to achieve expected code/functional coverage metrics. Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals. Work with FW team to convert DV sequence to FW drivers Support emulation, FPGA, prototyping efforts. Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts. Job Requirements Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS. 5 or more years of experience in ORAN protocol design verification using reference models. Hands-on experiences in integrating Python/C++ models to UVM environment and create Agents, Scoreboards components for network functional blocks. Experiences in Cadence vManager for DV metrics extraction and regression Good understanding of the complete verification life cycle (test plan, testbench through coverage closure). Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from scratch. Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell. Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based Experiences in GIT, JIRA, MS office suites Benefits: Competitive salary and stock options. Learning and development opportunities. Employer paid health Insurance. Earned, Casual, Sick & parental leaves.

ISSP FPGA prototyping delivers Intel's core products, therefore you will have a unique opportunity to take part in major activities that affect the entire organization and the high-tech world.Our FPGA design verification team is in charge of validating infrastructure designs used to prototype cutting edge Intel client, devices and data centers chips.We are looking for great, highly motivated problem-solvers seeking to make significant contributions and impact on the projects they work on.In your role you will plan, design and execute scalable and robust verification environments, learn complex digital computers flows and simulate the behavior of the RTL design in purpose of debug and development using advanced verification methodologies. Qualifications Studying towards a B.Sc. or MSc in Computer Science / Electrical Engineering / Computers Engineeringsome experience with OOP (C++, Java...)some understanding of chip design frontend flow (design/validation/synthesis)any relevant chip design / verification experience is a big advantage

o Pre-silicon verification of Intel's GPU IP, with focus on 3D and Memory Fabric. Qualifications o List top 3-4 skills required onlyStrong background in Logic Design and Computer Architecture. Desirable to have pre-silicon verification knowledge/tools such as system Verilog, pythonExperience using UNIX and Windows OS o Degree: o MS in VLSI/Electronics/Embedded/Compute Engineeringo Schools: Any Tier1 and Tier2 colleges with one year internship

Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP SoC handoff. Key Responsibilities: Design and develop cache architectures, including L1, L2, and L3 caches. Optimize cache performance, power, and area through innovative design techniques. Work closely with backend (BE) engineers to achieve timing closure and resolve any issues. Conduct static timing analysis (STA) and optimize the design for timing. Utilize lint, CDC (Clock Domain Crossing), and other design tools to ensure design quality and robustness. Implement and adhere to best practices in RTL design Collaborate with microarchitecture, RTL, verification, and physical design teams to ensure seamless integration of cache subsystems. Document design specifications, implementation details, and verification results. Participate in design reviews and provide feedback on other team members' designs. Qualifications Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. 5-15 years of proven experience in design and micro-architecture. Strong understanding of memory hierarchy, cache coherence, and performance optimization techniques. Proficiency in hardware description languages (HDL) such as Verilog or VHDL. Experience integrating BIST and DFT features into RTL designs. Experience implementing Error Correction Code (ECC) mechanisms in cache designs. Knowledge of error detection, correction, and recovery techniques. Experience with simulation and verification tools (e.g., ModelSim, VCS). Experience using lint, CDC, and other design tools to ensure design quality. Proficiency in static timing analysis (STA) and timing closure techniques. Familiarity with physical design constraints and considerations. Excellent problem-solving skills and attention to detail. Strong communication and teamwork abilities.

Job Description Work in a VLSI wireless team. Major subject VLSI, digital circuit, analog circuit. Project done on related topics preferably using CAD tools and familiar to ASIC design flow. Qualifications Degree: ME/M.TECH VLSI design, signal processing and machine learning, communication engineering Schools: NIT/VIT

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be responsible for RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires a deep understanding of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. Role & responsibilities Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality. Preferred candidate profile You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Master’s preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong understanding of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation.

Roles and Responsibilities Good communication and analytical problem solving capability. Should be having hing level understanding for Design, develop and test various types of antennas for various applications. Conduct research and evaluate the performance of novel antenna design CST/ HFSS/ MATLAB software skills are preferred Develop and maintain technical documentation, including test plans and reports Should have knowledge related to fabrication and testing of the designed antenna. Good communication and analytical problem solving capability. Hands-on experience on FPGA / RTL Design involving verilog HDL,Cadence, Vivado ISE/Xilinx ISE, Modelsim and Synopsys will be an added advantage. Desired Candidate Profile B.E. or B.Tech with minimum one year of work experience. M.E. or M.Tech fresher. Perks and Benefits Salary, monthly grocery and medical insurance.

As a member of the G&E SoC DFT Team, the successful candidate will own the DFT RTL integration and MBIST responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture MBIST/SMS Insertion at Tile/Block level MBIST/SMS Verification at Tile/Block levle and SoC level Experience in memory BIST architecture , memory repir and efuse Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

As a member of the G&E SoC DFT Team, the successful candidate will own the DFT responsibilities for the next gen of AMD SoCs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

Qualification: Preferably an Electronics / Electrical engineer with a good working knowledge of instrumentation and very demonstrative writing skills. Job Description: This position handles technical communications of the projects, in constant interaction with various departments and the customer. Also should maintain various company documents like HR manual, Standard template for presentations etc. ? Assist the Design and Development Team with the following documents in the required standard format. o Technical Specifications Document o Master Drawing Index o Quality Assurance Plan o User Manual o Release Note o API help o Installation guides o Product Datasheets & Brochures o Any other documentation requirements that emerge from client to client Experience / Requirement Hands on experience in Technical Writing for at least 5 years in the following areas o Technical Writing o Content Management o Content Strategy o Technical Documentation o Project Coordination o Research and Innovation o API Documentation o SOP Development Should have complete knowledge of at least one of the following standards. o DO-254 (HW) o DO-178 (SW) o DOD 2167A o MIL 498 o MISRA Other requirements (preferable not vital) o Should have some experience of coding VHDL/Verilog and C/C++ o Should have managed a team of Technical Writers Roles & Responsibilities: This position plays a pivotal role in the project executions, by preparing all the deliverable and non- deliverable documents of the project. Thus an amiable disposition that would elicit the required inputs and convert these technical inputs into readable matter with proper traceability that would help the user to reach out to the information sought directly and with clarity. The standards used may change from project to project, depending on the contractual obligations and customer requirements. The technical writer should participate in the document reviews with the customer and the project team to resolve the customers observations. Should be willing to travel and meet with customers in all parts of India and abroad. Compensation: As per Industry Standards

Job Description : - Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA). - Should be excellent in DDR protocol knowledge. - Must be an expert in micro architecture and RTL coding. Skill set needed - Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.) Scripting : (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up. What You'll Do: - You will be responsible for pre-sales support, proposing architecture to customers based on their requirements. - You will work with team to come up with architecture and micro-architecture and work with cross functional team to ensure delivery - You will manage the design / RTL team to achieve the project goals - You will work with customer, provide technical support and provide collaterals agreed upon - You will work with team to achieve flow, methodology improvements to achieve high reuse - You will work with IP vendors to generate / get right configurations of the IP - You will manage team work allocation, schedule, risk mitigation and deliverables from design team. What You'll Need: - 4+ Years of experience in understanding of ARM based architecture, CPU subsystems, interconnect, boot process, memory subsystem, knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks - Good understanding of IPs, integration/application requirement, work with RTL team/vendors to achieve architecture goals - Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe, DDRx, USB, SATA, . - Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect solutions available - Should have good understanding of process / flow to achieve power & performance goals - Should understand and work on all aspects of VLSI development from SoC architecture, micro architecture, RTL coding, RTL quality checks, silicon bring up. - Should have good understanding of requirements from physical design, FPGA, Software, DFT and verification team. - Should have handled a design from Spec to GDS-II - Track design progress, working with cross functional teams, delivering on agreed upon milestones. - Should provide mentoring and support to the team

The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture DFX timing constraints development Review timing reports Timing closure for different modes : AC/DC scan capture , scan shift , MBIST Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Proficient in logic design using Verilog Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

The candidate must have thorough knowledge of DFT basics such as DFT RTL insertion. scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug. Interfacing with the design teams to ensure DFT design rules and guidelines are met Interact with PD and Front End Integration team for Scan Insertion Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model Simulating and verifying the ATPG and LBIST patterns Working with the product engineering teams on the delivery of manufacturing test patterns Developing, enhancing and maintaining scripts as necessary Able to technically guide and mentor junior folks in the team PREFERRED EXPERIENCE: Experience in creating and implementing complex chip-level DFT architecture Proficient in logic design using Verilog Experience in DFT implementation including Scan insertion, ATPG and Simulations Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression Experience in debugging low coverage and DRC fixes Experience of debugging test pattern issues Support the Silicon bringup activities to guarantee highest stability of the test pattern Knowledge of MBIST is a plus. Knowledge of synthesis is a plus Experience with post-silicon debug Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc Any Tessent Scan/ATPG certifications is a plus Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Prior experience as DFT engineer

Job Title: Member of Technical Staff (MTS) DFT Verification Experience: 6+ years Location: Bangalore Job Description: We are seeking a dedicated and experienced Member of Technical Staff (MTS) specializing in DFT Insertion and Verification . The candidate will play a key role in ensuring the robustness and reliability of Tile and SoC designs by implementing and verifying advanced test architectures. Key Responsibilities: Perform SMS (Structural Mode Scan) Insertion and verification at both Tile and SoC levels. Design and verify Memory BIST (Built-In Self-Test) architectures, including initialization and integration. Implement and validate memory repair strategies, including fuse programming (eFuse) and redundancy management. Debug and optimize DFT flows to meet high fault coverage and manufacturability standards. Collaborate with cross-functional teams to ensure seamless DFT integration across various design phases. Analyze test results, resolve silicon and test-related issues, and contribute to yield improvements. Required Skills: Expertise in SMS Insertion and verification for Tile and SoC level designs. Proficiency in Memory BIST architecture, including repair mechanisms and eFuse configuration. Hands-on experience with DFT tools like Mentor Tessent, Synopsys DFT Compiler, or Cadence Modus. Strong scripting skills in Python, Perl, or TCL for automation of test flows. Knowledge of RTL design and debugging (Verilog/VHDL). Excellent problem-solving and analytical skills, especially in debugging silicon failures. Preferred Qualifications: Experience with low-power DFT methodologies and advanced compression techniques. Familiarity with industry standards for JTAG and boundary scan. Hands-on experience with post-silicon validation, bring-up, and characterization.

About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications Minimum Qualifications:BS+15 Years of relevant experience in the semiconductor I industry. experience15+ years of experience in/withVerilog and system verilog, synthesizeable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 10+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Description: As a Design Verification Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high-speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will need to have the ability to work as a Design Verification Engineer, to evaluate Full chip or block level functionality and provide solutions to help delivery of functionally correct design. You will work closely with Micron's various design and verification teams all over the world to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries to specific designs as needed. Responsibilities will include, but not limited to: Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. • Good knowledge of Basic Analog/Digital concepts. • Good knowledge of Verilog/SV concepts. • Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview. • Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues. • Work experience in co-sim simulation designs is a plus. • Good scripting skills using perl, python is a plus. • Must possess good communication skills and ability to work well in a team. Bachelor's with 2+ years of work experience or Post Graduate Degree in Electronics Engineering or related engineering field with 1-2 years of working experience is required.

About Marvell . Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Responsible for IP/Subsystem Verification. Define Test Plan, Testbench Architecture, and develop testbenches. Execute Design Verification (Testbench/test sequence development, debug, regression, coverage closure, gate-level simulations). Support Silicon bring-up activities. Debug failures in simulation and perform root-cause analysis What We're Looking For Bachelor s or Master s degree in Computer Science, Electrical Engineering with 8+ years of experience in Digital Pre-Silicon Verification. Experience in leading IP, Subsystem, or SoC-level verification. Strong understanding of SoC/Subsystem design verification concepts and architectures. Hands-on experience with Verilog, SV-UVM, and SoC-level testbenches. Experience in setting up and debugging functional and gate-level simulations. Ability to translate functional requirements into verification plans. Proficiency in developing verification environments and regression setups. Expertise in coverage analysis and closure. Strong interpersonal and communication skills. Ability to collaborate and influence design verification methodologies. Quick adaptability to new technologies with strong problem-solving skills. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

Analog Mixed Signal Layout Location: Bangalore, Hyderabad, Noida Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Experience (years) : 3 - 7 Years Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

About Astrogate Labs Astrogate Labs is a space-technology start-up based in Bengaluru, building core technologies in laser communication terminals and networks for small-satellites. Astrogate Labs aims to simplify, reduce cost of communication, and enable satellites send more data to ground. We have developed one of the industry s smallest optical communication terminals targeted for small satellite use, further scaling our products and aiming for our first satellite mission. We aim to revolutionize satellite communications and support the growing satellite downlink needs with a network of optical ground stations and in-space relays using the technologies developed in-house. We are looking for bright and passionate folks like you to join our exceptional team. Job Title: FPGA Design Engineer Qualification: ME/MTECH in Electronics & Communication or Electrical engineering or any other related field with 3+ years of relevant experience, although this is secondary to relevant experience. Job Responsibilities: We are looking for folks who is excited to work with corss-functional team and develop custom FPGA module/ cores for our laser/ optical communication systems. Design, Implement, Test and Integrate RTL FPGA hardware for free space laser/ optical communication applications. Write custom FPGA IP blocks and PS code for target hardware. Write testbenches to test the target hardware by integrating other system peripherals. Integrate designs onto FPGA/SoC platforms Bring up and validate devices that communicate to and fly in space Digital signal processing of sensor data. Participate in component selection and design tradeoff analysis. Document and manage configuration of firmware Contribute to peer and external design reviews Required Skills/Experience: 2+ years of experience in FPGA Design, Implementation & Verification. Proficient with Verilog/VHDL Experience in FPGA Implementation Tools (XILINX Vivado), Zynq SoC s. Deep understanding of digital design concepts, communication systems, various modulation, encoding & forward error correction techniques. Good knowledge in C/C++ and MATLAB Experience with simulation, verification, and test of FPGA firmware and embedded systems Hardware debug experience, including familiarity with tools such as the oscilloscopes, logic analyzers, and signal generators. Familiar with common electronic components and comfortable reading circuit design schematics and contributing to electronics hardware design discussions Must be an independent thinker and motivated to work within a multidisciplinary team. Perks: Health Insurance coverage Association & supervision by industry experts and senior members. Publish research on behalf of Astrogate Labs Other early-stage company benefits including ESOPs Team oriented work culture for the development of extraordinary space products Prior experience in aerospace/ space technology projects is an added advantage. If you like working in a fast paced environment in a multi-disciplinary team on developing and maturing state-of-the-art Lasercomm systems, then this role might be for you.

We are looking for an experienced Engineer with extensive experience with FPGA and emulation tasks of SoC preferably for Power related applications that has a thorough understanding of Xilinx Architecture and Timing closure strategies with the Verilog RTL coding skills and debug capabilities Exp-7