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Iitjobs Inc.
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Senior Design Verification (DV) Engineer Pre-Silicon DV

Senior Design Verification (DV) Engineer Pre-Silicon DV

Iitjobs Inc.

8 - 12 years

15 - 30 Lacs

ahmedabad bengaluru

Posted:21 hours ago| Platform:

Apply

Skills Required

verilog ip uvm

Work Mode

Work from Office

Job Type

Full Time

Job Description

Senior Design Verification (DV) Engineer Pre-Silicon DV

Location:

About the Role

Senior Design Verification Engineer

Key Responsibilities

Verify various
IP modules and SoC-level components
.
Develop and implement
simulation testbenches
, low-power simulation setups, assertion checkers, and coverage monitors.
Create and maintain
UVM-based SystemVerilog testbenches
.
Develop
C/Assembly diagnostics
, analyze coverage data, and debug simulation failures.
Contribute to
test plan creation
, feature bring-up, and coverage closure.
Work independently or in collaboration with cross-functional teams.

Required Qualifications & Skills

8+ years of hands-on design verification experience.
MS (or higher) in
EE/EC/ECC Engineering
.
Strong knowledge of
computer architecture
and DV fundamentals.
Expertise in
Verilog, SystemVerilog, SVA
, and industry-standard EDA simulation tools.
Proven experience with
UVM methodology
and complex testbench development.
Hands-on experience with
AMBA protocols
,
Bluetooth MAC
, and
Wi-Fi 802.11 MAC
.
Experience with
PCIe MAC
or
USB MAC
(deep protocol-level exposure accepted).
Strong background in
Low-Power Simulation
,
UPF setup
, and debugging LP issues.
Proficiency in scripting languages such as
Perl
or
Unix Shell
.
Experience with assembly language programming is a plus.
Excellent written and verbal communication skills.

Work Location

Ahmedabad
or
Bangalore
(India)

Why Apply?

Opportunity to work on cutting-edge verification projects.
Fast onboarding – join within 15 days!
Attractive
50,000 referral bonus
for successful candidate referrals.

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