2321 Verilog Jobs - Page 47

Basic Job Deliverable Silicon Design Engineer (RTL Design and Development) Responsible for RTL design and development Responsible for generating documents, such as requirements specification, design, user-guide, etc., Experience: Experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools Experience with Ethernet/PCIe/SPI/I2C/USB/GPIO/Memory architectures /DDR/SDRAM/DMA technologies Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Strong debugging skills at device and board level Scripting language experience like Perl, Python or TCL Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Qualification: B.Tech/M.Tech (CSE/ECE/EEE) - Track record of high academic achievement Interested candidates, please share your updated resume to althia.pereira@smartsocs.com

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

Experience in construction, foundations, and maintenance work Project execution and quality checks Bill checking, rate analysis, BOQ preparation Bar chart preparation and coordination with team KeyResponsibilities: Handle industrial construction projects Execute and inspect work as per project requirements Assist in bill verification and BOQ tasks Support maintenance and ongoing project work Prepare progress reports and ensure team coordination

Role & responsibilities FPGA, RTL, DO-254,VHDL, VERILOG, XILINX, LIBERO, AVIONICSJ Preferred candidate profile

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER As a member of the AECG Product Validation and Solutions Team within AMD you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. The Role At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen 6, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. The Person You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. Key Responsibilities Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans Pre-Silicon and Post Silicon validation for new PCIe enabled blocks Responsible for IP design, Silicon bring up, Validation and IP release Work in collaboration with the Global teams Preferred Experience Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog Proficient in RTL simulation tools (VCS, Modelsim) Knowledge of high-speed interfaces including, PCIe, CXL, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer Experience in developing system or IP prototypes using FPGAs Strong knowledge of IP/SOC design methodologies Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles Knowledge of C/C++ is an added advantage ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 8+Yrs of exp Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary The candidate will be responsible for working in the formal verification domain, specifically targeting designer applications within JasperGold. Additionally, the candidate will contribute to machine learning initiatives into designer apps. Candidate should have 1 -2 years of experience and be proficient in C++ with a strong understanding of data structures and algorithms. Knowledge of Verilog, VHDL and Qt is a plus. We’re doing work that matters. Help us solve what others can’t.

Experience: 5+Years Job Location : Hyderabad The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable). · Knowledge of invoking the MATLAB DPI checker (or any foreign language) in the UVM

Job Description: We are seeking a skilled and motivated DFT Engineer with at least 2 to 10 years of industry experience in Design for Test in the VLSI domain. As part of our SoC Design team, you will play a key role in implementing and validating DFT architecture to ensure high test coverage, low DPPM, and efficient silicon debug capabilities. Key Responsibilities: Develop and implement DFT architecture for complex ASICs and SoCs. Integrate and verify DFT features such as: Scan insertion and ATPG Memory BIST (MBIST) Logic BIST (LBIST) JTAG/IEEE 1149.1 (Boundary Scan) Test compression techniques (e.g., Tessent, Synopsys DFTMAX) Work closely with RTL, synthesis, and backend teams for DFT implementation and sign-off. Run and debug simulations for scan and BIST logic. Work with Automatic Test Equipment (ATE) teams to bring up and validate silicon. Support post-silicon debug and yield improvement efforts. Collaborate with cross-functional teams including verification, physical design, and validation. Required Skills: 2+ years of hands-on experience in DFT implementation and test methodology. Strong knowledge of scan insertion, ATPG, and fault grading. Experience with DFT tools such as: Synopsys (DFTMAX, TetraMAX) Mentor Tessent Cadence Modus Proficiency in Verilog/VHDL, TCL, and shell scripting. Understanding of digital design and SoC architecture. Familiarity with STA and timing constraints related to DFT.

Key Responsibilities: 1. Design and Development: Partition algorithms for implementation in FPGA and/or software. Identify building blocks and signal processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory requirements. Define the architecture of RTL functions and create module-level details from architecture to coding and simulation. 2. Project Ownership: Manage projects from concept to delivery, including risk identification, dependency management, mitigation planning, and tracking project schedules. Conduct design reviews and hold discussions with customers to ensure alignment. 3. Verification and Validation: Apply methodologies for design, verification, and validation. Conduct peer reviews of designs and simulations. 4. Documentation: Define, create, and maintain project-related documentation, including design documents and detailed analysis reports. 5. Customer Interaction: Understand customer requirements, specifications, and tender inquiries. Define system, and board architectures based on requirements. 6. Support: Provide customer support during integration phases at test sites. Assist production teams as needed. Minimum Service Agreement : 12 Months Service

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP Sales and Distribution (SD) Good to have skills : Pricing Analytics and ModellingMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will design, build, and configure applications to meet business process and application requirements. Your day will involve collaborating with teams to develop solutions and ensure seamless application functionality. Roles & Responsibilities:-Responsible for analyzing business/technical needs and translating process into practice through the current Information Technology tool sets. The role will also implement new solutions through configuration and creation of functional specifications and facilitate solution realization. In addition, the role will have responsbilities for conducting testing and trouble shooting solutions.- Analyze business/technical needs and translate process into practice through the current Information Technology tool sets.- Implement new solutions through configuration and creation of functional specifications and facilitate solution realization.- Conduct full integration testing of new or changed business/technical processes. Develop business/technical cycle tests for use by stakeholder community. Document all process changes and provide knowledge to relevant stakeholders- Troubleshoot, investigate and persist. Develop solutions to problems with unknown causes where precedents do not exist by applying logic and inference with creativity and initiative. Provide cross-functional support and maintenance for responsible business/technical areas.- Conduct cost/benefit analysis through evaluation of alternative design approaches to determine best-balanced solution. Best-balanced solution is one that satisfies the immediate stakeholder needs, meets system requirements and facilitates subsequent change.- Assume leadership role in a small size initiatives by playing the key contributor, facilitator or group lead. Professional & Technical Skills: - Must To Have Skills: Proficiency in SAP Sales and Distribution (SD)- Good To Have Skills: Experience with Pricing Analytics and Modelling- Strong understanding of SAP SD modules and functionalities- Experience in customizing and configuring SAP SD applications- Knowledge of integration with other SAP modules- Ability to troubleshoot and resolve technical issues efficiently Additional Information:- The candidate should have a minimum of 5 years of experience in SAP Sales and Distribution (SD)- This position is based at our Hyderabad office- A 15 years full-time education is required Qualification 15 years full time education

We are looking for a highly skilled and experienced Branch Receivable Manager to join our team at Equitas Small Finance Bank. The ideal candidate will have 7-10 years of experience in the BFSI industry, with expertise in Assets, Inclusive Banking, SBL, Mortgages, and Receivables. Roles and Responsibility Manage and oversee branch receivables operations for efficient cash flow. Develop and implement strategies to improve receivables management. Collaborate with cross-functional teams to resolve customer issues and enhance service quality. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Lead and motivate a team of receivables professionals to achieve business objectives. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, and receivables. Excellent leadership and communication skills. Ability to analyze data and make informed decisions. Strong problem-solving and customer service skills. Proficiency in financial software and systems.

Knowledge of Analog and Digital Circuit Design, Verilog, System Verilog, VHDL, FPGA, CMOS. Hands on experience with Simulation and Verification, Timing and Power Analysis industry Standard Tools. Knowledge of Electronic Design Automation tools

Role : Design Verification Engineer Location: Hitech city ,Hyderabad Qualification: Bachelor's Degree Experience : 2-6 years of professional experience. Work Mode : Work from office, 5 days a week. Job Description Strong Familiarity with System Verilog and OVM/UVM Verification Methodology. Knowledge of system-level architecture including buses like AXI/AHB/APB/ACE5 Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, Model Sim . Proficiency in developing the TB environment Good Knowledge on writing coverage and assertions Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process Knowledge on the PCIE is required. Knowledge of mipi, video Ips like ISP/Encoder/Decoder would be useful. Functional Skills Ability to work with cross-functional teams

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications. Location: Mayiladuthurai,Chidambaram,Cuddalore,Tittakudi

We are looking for a highly skilled and experienced Branch Receivable Officer to join our team at Equitas Small Finance Bank. The ideal candidate will have 1-4 years of experience in the BFSI industry, preferably with a background in Assets, Inclusive Banking, SBL, Mortgages, or Receivables. Roles and Responsibility Manage and oversee branch receivables operations for timely and accurate payments. Develop and implement strategies to improve receivables management and reduce delinquencies. Collaborate with cross-functional teams to resolve customer complaints and issues. Analyze and report on receivables performance metrics to senior management. Ensure compliance with regulatory requirements and internal policies. Maintain accurate records and reports of receivables transactions. Job Requirements Strong knowledge of BFSI industry trends and regulations. Experience in managing assets, inclusive banking, SBL, mortgages, or receivables. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Proficiency in Microsoft Office and other relevant software applications.

Company Description RV Skills Design Centre, formerly known as RV-VLSI, is a premier VLSI, Embedded Systems, and AI skill development center established in 2006 by the RV group of educational institutions. Managed by industry-experienced professionals, RV Skills offers innovative full-time and part-time programs to enhance the employability of engineering graduates and working professionals. As a trusted partner for industry hiring and training, the center has established a benchmark for skill development programs in India through collaborations with EDA vendors, foundries, and industry experts. Role Description This is a full-time on-site role for a Design Engineer, based in Bengaluru. The Design Engineer will be an experienced and passionate RTL Verification Trainer to design, develop, and deliver training programs focused on RTL (Register Transfer Level) design verification methodologies. The ideal candidate should have a strong background in ASIC design verification, proficiency in industry-standard tools, and a solid understanding of verification techniques such as UVM, System Verilog, and functional coverage. The trainer will be responsible for upskilling fresh graduates, and industry professionals. Key Responsibilities Design and deliver structured RTL verification training modules tailored for varying expertise levels (beginner to advanced). Develop hands-on lab sessions, real-world case studies, and projects to enhance practical understanding. Conduct live instructor-led training sessions. Evaluate training effectiveness through assessments, feedback, and performance monitoring. Stay updated with the latest verification trends, tools, and methodologies, and continuously refresh training materials. Provide mentorship and technical support to trainees during and after the training sessions. Develop certification exams to benchmark trainee competencies. Document training materials, presentations, lab manuals, and FAQs. Required Skills and Qualifications Bachelor’s or Master’s degree in Electronics, Electrical. Experience in RTL verification, preferably in ASIC/FPGA domains or teaching in any institute. Strong expertise in: Verilog and digital circuits SystemVerilog for verification, UVM(optional) RTL simulation tools (e.g., Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa) Previous experience in training, mentoring, or technical leadership is a strong plus. Excellent communication, presentation, and interpersonal skills. Ability to simplify complex concepts and adapt to various learning styles. Please sending your resumes to info@rv-skills.com.

Role: Senior Design Verification Engineer (PCIe) Role: Bangalore Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, score boarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in System Verilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, Sim Vision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers Job Types: Full-time, Permanent Pay: ₹4,000,000.00 - ₹5,000,000.00 per year Benefits: Cell phone reimbursement Health insurance Paid time off Provident Fund Schedule: Day shift Work Location: In person

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Digital design skills (RTL, Verilog, good digital design skills, Integration experience) QC and Implementation experience (Linting/Spyglass, CDC, Synthesis, Constraints development, LEC, GLS debug, PD interactions) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 5-7 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #DVT

About Company Espressif Systems (688018) is a public multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power IoT solutions. We have created the popular ESP8266 and ESP32 series of chips, modules and development boards. By leveraging wireless computing, we provide green, versatile and cost-effective chipsets. We have always been committed to offering IoT solutions that are secure, robust and power-efficient. By open-sourcing our technology, we aim to enable developers to use Espressif’s technology globally and build smart connected devices. In July 2019, Espressif made its Initial Public Offering on the Sci-Tech Innovation Board (STAR) of the Shanghai Stock Exchange (SSE). Espressif has opened a Technology Center in Pune (Baner), India, which will focus on embedded software engineering and IoT solutions development for our growing customers. About Role Job Responsibilities Digital IP design Perform Lint/CDC/LEC/DFT/Low-Power analysis Module level synthesis and timing constraints Must have worked on ARM/RISC-V CPU based designs Familiarity with FPGA/Silicon validation using C based tests and usage of standard debugging tools Qualifications M.Tech/B. Tech in the field of VLSI/Electronics engineering with 4 to 8 years of experience. Proficiency in System Verilog for RTL logic design and verification. Strong understanding of CPU pipeline and computer architecture is a must. EDA tool knowledge of Design Compiler, PrimeTime is preferred. Automation skills in PERL and/or TCL and/or Shell* is an added plus. Team player, with good problem solving and communication skills. What to expect from our interview process The first step is to email your resume or apply to the relevant open position, along with a sample of something you have worked on such as a public GitHub repo or side project etc. Next, post shortlisting your profile recruiter will get in touch with you via a mechanism that works for you e.g. via email, phone. This will be a short chat to learn more about your background and interests, to share more about the job and Espressif, and to answer any initial questions you have. Successful candidates will then be invited for 2 to 3 rounds of technical interview as per previous round feedback. Finally, Successful candidates will have interview with HR. What you offer us Ability to provide technical solutions, support that fosters collaboration and innovation. Ability to balance a variety of technical needs and priorities according to Espressif’s growing needs. What we offer An open minded, collaborative culture of enthusiastic technologist. Competitive salary. 100% company paid medical/dental/vision/life coverage. Frequent trainings by experienced colleagues and chances to take international trips, attend exhibitions, technical meetups and seminars.

Location Karnataka Bengaluru Experience Range 5 - 10 Years Job Description PFB the JD. JD Lead: 1 or 2 or 3 based on the options we get 15+ years of experience in Design Verification Strong experience in Processor based SoC verification Strong experience in ARM Cortex M or A series designs. Must have worked on bringing up the boot code, writing ISR, exceptions and other functions Strong experience in System Verilog and UVM based design verification Experience in Tensilica xtensa designs is a big plus Must have lead at least 2 to 3 SoC DV or Processor subsystem projects with a team size of 10+ Engineers Must have strong experience in AMBA protocols Must have strong understanding of functioning of Cache controllers, DMA & memory management controllers/ techniques JD Engineer: 9 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must 3. Experience in writing C or Assembly testcases is a must 4. Strong experience in AHB or AXI protocol is a must 5. System Verilog and UVM experience is a must JD Engineer: 6 members 1. 3 to 10 years of experience in Design Verification 2. Good experience in Processor based SoC Verification is a must OR strong experience in IP verification using SV/ UVM is a must 3. Experience in writing C or Assembly testcases is a plus 4. Strong experience in AHB or AXI protocol is a must Location: 1. Pune or Noida or Bangalore 2. Each location needs a lead + team of 3 to 4 to a minimum 3. If we can set it up in one location that would be great

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you? We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your career meets tomorrow. Looking for Siemens EDA Ambassadors- QuestaSim (Simulation) R&D team (strong AI/ML background) This is your role In this role, you will, craft and develop AI/ML-driven algorithms and solutions to improve simulation tools' performance and capabilities. Contribute to building state-of-the-art engines and components, integrating machine learning techniques into simulation and verification workflows. Contribute to the development and improvement of production-quality components, algorithms, and engines while supporting and improving existing codebases. Solve complex, open-ended problems in collaboration with a senior group of engineers in a fast-paced and multifaceted environment. Apply technical expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies to achieve project milestones. Stay self-motivated, disciplined, and focused while driving innovation within the team. Required Qualifications We are seeking a graduate with Bachelor’s or Master’s degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field from an accredited institution. We value your experience with conceptualizing, defining, architecting, and implementation of an open-ended problem scope or new insights. Hands-on experience with AI/ML techniques, including supervised and unsupervised learning, neural networks, and reinforcement learning. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Knowledge of machine learning and deep learning frameworks. Strong understanding of Compiler Concepts, Optimizations, and parallel computing. Experience working on UNIX and/or LINUX platforms. Excellent problem-solving and analytical skills. Proven track record to work independently, take ownership of tasks, and deliver results A plus! Basic knowledge of Digital Electronics and concepts related to SystemVerilog, Verilog, and VHDL. Exposure to Simulation technologies or Formal-based Verification methodologies is a plus! We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.