2321 Verilog Jobs - Page 48

ASIC DFx - MTS Silicon Design Engineer New Dehli, India Engineering 66377 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Senior IP / Sub System & SOC Verification Engineer with NLP simulation Bangalore, India Engineering 66695 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SE NIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: SOC NLP & Power Management): Work on SOC level verification activities, the person will be responsible for bringup of UPF simulation at SOC. Work with testbench team to bringup NLP (UPF) simulation, debug simulation issues. He will be responsible to coordinate with Design team for UPF delivery, work with design (IP, Subsystem, SOC) for quality UPF delivery and resolve issues. He should have good understanding of power architecture and UPF’s He will be responsible to create TB collaterals for NLP simulation bringup. THE PERSON: Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for SOC testbench, Power management, UPF, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions. KEY RESPONSIBILITIES: NLP Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team) Power verification is key responsibility. Work with power architects to resolve issues seen in simulation. PREFERRED EXPERIENCE: Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. NLP Simulation is must requirement. Strong hands-on experience in different SOC Verification activities, NLP Simulation, Power verification, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. ACADEMIC CREDENTIALS: BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-8 years of strong DV experience in NLP simulation, IP, Sub System & SOC Verification, Power management verification #LI-SR4 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science. Experience working with architecture, design, and implementation of digital logic using Chisel. Knowledge of accelerators (e.g., Machine Learning or GPUs) or similar high performance designs. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Use simulation/emulation/power analysis tools and techniques to ensure power and performance meet defined specifications. Develop, implement, and maintain design blocks or components/part of a hardware product, and integrate design blocks or components/parts to create product subsystems. Engage with Verification and Silicon Validation teams to ensure functionality of the design. Provide input on synthesis, timing closure, and Physical Design of digital blocks. Take a leadership role on technical project teams and set technical direction. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture. Experience in handling low power schemes, power roll up and power estimations. Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC). Experience with Perl or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. Experience with methodologies for low power estimation, timing closure, and synthesis. Experience with computer architecture. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience with accelerator architectures and data center workloads. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years of experience post PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Knowledge of high performance and low power design techniques. About the job In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations. Use AI techniques for faster and optimal Physical Design Convergence -Timing, floor planning, power grid and clock tree design etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. About The Job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with performance, power, and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design and more to specify and deliver high quality designs for next generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Own implementation of IPs and subsystems. Work with Architecture and Design Leads to understand micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance, and Area improvements for the domains. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Job description: Architecture and design of digital blocks for integration CMOS IC’s Specification and design of digital blocks at RTL level and addition of DfT concept onto the design Synthesis, block verification and gate level analysis of implemented digital blocks for on-silicon integration Implementation and verification of ECO’s on existing designs Technically lead digital design tasks in strong cooperation with project technical lead and project manager Creation and patenting of new IP Profile description: Successfully completed university degree in Electronics or comparable Extensive years of experience in digital design with hands-on experience on relevant design/simulation/synthesis tools Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices. Knowledge of relevant digital design flow tools for synthesis, LEC (logic equivalence check), CDC/RDC (clock/reset domain crossing), linting, synthesis constraining Knowledge of advanced digital verification tools and methodologies (e.g UVM) would be a plus Strong team player, committed to deadlines and development discipline, with a visible “what’s best for the company” mentality Soi Kim Kee suki.kee@ams-osram.com +65 () 62402395

Hyderabad, Guntur Strong Verification experience at Subsystem or SOC level Strong in System Verilog, Verilog, UVM, C/C++, Scripting Strong debugging skills, problem solving skills. Good attitude , good team player with strong interpersonal skills Power Management, Graphics Domain experience preferred Candidate must have low power verification experience in intel(ODC)/AMD(ODC) projects. Academic Qualification BTech / Mtech Electrical/Electronics/Computers Experience 5-10 years Interested ? Apply now! USE LINKEDIN PROFILE Enter your full name* Enter Email* Enter LinkedIn profile link* Attach Your Resume (Max size 4MB)* SUBMIT or APPLY HERE

Job Summary: We are seeking a highly skilled and motivated Senior Design Verification Engineer to join our growing team. You will be responsible for planning and executing the verification strategy for complex ASIC/SoC designs. You will work closely with design, architecture, and software teams to ensure functional correctness of RTL through rigorous verification methodologies. Key Responsibilities: Develop and execute comprehensive test plans based on design specifications and architectural documents. Build and maintain constrained-random verification environments using SystemVerilog UVM . Write testbenches, test cases , and functional coverage to ensure design quality. Debug RTL and testbench issues using industry-standard tools (e.g., VCS, ModelSim, Verdi, DVE). Develop and track coverage metrics (code, functional, and assertion coverage). Contribute to the automation of the verification process (e.g., regression tools, continuous integration). Participate in design and verification reviews and provide technical guidance to junior engineers. Required Skills & Experience: Bachelors or Masters degree in Electronics, Electrical Engineering, or Computer Engineering . 3Years to 25 Years of experience in RTL verification of complex digital designs. Proficiency in SystemVerilog , UVM methodology , assertions, and functional coverage. Strong debugging and problem-solving skills. Experience with simulation tools (Synopsys VCS, Cadence Incisive/Xcelium, ModelSim, etc.). Solid understanding of SoC architecture, AMBA protocols (AXI, AHB, APB). Hands-on experience with scripting (Python, Perl, Tcl, or Shell). Familiarity with version control systems (e.g., Git, Perforce). Preferred Qualifications: Exposure to PCIe, Ethernet, USB, DDR , Jtag or other high-speed interfaces. Why Join Us: Work on cutting-edge technology with top-tier semiconductor clients. Opportunity to lead verification activities and mentor junior team members. Competitive compensation and flexible work culture.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER THE ROLE (SOC Verification Engineer: SOC NLP & Power Management): Work on SOC level verification activities, the person will be responsible for bringup of UPF simulation at SOC. Work with testbench team to bringup NLP (UPF) simulation, debug simulation issues. He will be responsible to coordinate with Design team for UPF delivery, work with design (IP, Subsystem, SOC) for quality UPF delivery and resolve issues. He should have good understanding of power architecture and UPF’s He will be responsible to create TB collaterals for NLP simulation bringup. The Person Engineer with strong self-driving ability. Need excellent communication skills (both written and oral) Strong problem-solving skills, go to person for SOC testbench, Power management, UPF, C/C++ Coding, UVM coding, Testcase coding, checkers and assertions. Key Responsibilities NLP Simulation bringup (Has responsibility of TB, Testcase, coordination between design and dv team) Power verification is key responsibility. Work with power architects to resolve issues seen in simulation. Preferred Experience Expertise in IP, Subsystem and SOC Verification with specialization in NLP Simulation. NLP Simulation is must requirement. Strong hands-on experience in different SOC Verification activities, NLP Simulation, Power verification, UVM, System Verilog, X86, C++, HW/SW co-verification, Scripting (phython) Test plan review, Debug/triage, Coverage, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, DDR, memory controller etc. Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc. Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence. JIRA based project management is a plus. Academic Credentials BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE 5-8 years of strong DV experience in NLP simulation, IP, Sub System & SOC Verification, Power management verification Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ AECG ASIC DFx - MTS SILICON DESIGN ENGINEER The Role AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. THE PERSON: As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives, this role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team! KEY RESPONSIBILITIES: Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications. Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS, ATPG and Scan GLS. Work with multi-functional teams and handling schedules Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 8 years of DFT or related domains experience, leading DFT efforts for large processor and/or SOC designs is a plus. Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Good understanding of RTL quality checks such as SGLINT, SGDFT, CDC, RDC etc Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. is a plus Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

ALTEN Calsoft Labs expertise in VLSI services can transfer your product ideas into cost-effective System on Chip (SoC) designs for Networking, Mobile Multimedia and Consumer Electronics solutions with a faster time to market. Some of the key highlights of our Semiconductor Practice include - Multiple engagements with Tier-1 silicon vendors and fabless semiconductor companies from Spec-to-Netlist Focus on latest verification methodologies - OVM, VMM and UVM Verification & validation experience of complex SOC designs up to 28 nm process technology Expertise in implementing complex ASICs in 130nm, 90nm, 65nm & 40nm Skills:- uvm, systemverilog, rtl, semiconductor, cdc, lint, Verilog and VLSI

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What You’ll Be Doing Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What We Need To See B.Tech./ M.Tech or equivalent experience 5+ years of relevant experience Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) Experience in developing and working in functional coverage based constrained random verification environments Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways To Stand Out From The Crowd Excellent knowledge of PCIE protocol - Gen3 and above Good understanding of the system level architecture of PCIE/CXL-based designs Perl, Python or similar scripting and SW programming language experience Good debugging and analytical skills Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1998093

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

SMTS Silicon Design Engineer Bangalore, India Engineering 66762 Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Lead Verification Engineer THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as well as in a cross-site team environment ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SILICON DESIGN ENGINEER 2 (AECG ASIC - SoC verification Engineer) The Role The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 2+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench under supervision from team lead. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification will be a plus Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SOFTWARE DEVELOPMENT ENGINEER The Role AMD is looking for a talented, self-driven and motivated engineer to technically lead AIG’s Simulation Modeling projects working on AMD’s XDNA (AI Engine) architecture and the Vitis AI family of software tools. The XDNA is an industry leading architecture in terms of performance per watt and is used in AMD’s client and embedded devices as the primary engine for Machine Learning workloads. It is the hardware engine behind Windows Co-pilot on AMD devices. The team provides a fast-paced environment offering each of its members immense opportunity to interact with a wide variety of people including from other organizations like hardware designers, marketing, support, and even direct customer interaction, and truly learn and grow their skills and capabilities. The Person The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated technical issues to resolution. They should have demonstrated ability to identify technical problems, explore and propose viable options, and apply technical solutions. They should be able to excel in a global team environment with strong verbal and written communication skills. Key Responsibilities Vitis AI is AMD’s primary SDK that enables users to compile and run their ML models on the XDNA architecture. As a senior member of this high-performance team, the selected candidate will have responsibility to model the XDNA architecture in terms of functionality, accuracy and simulation speed. Candidate will work with compiler, runtime/driver teams to bring up latest AI models like CNNs, Transformers, StableDiffiusion, NLPs etc. on the XDNA simulator. This is a crucial part of AMD’s shift-left strategy for the successful bring up of new devices and day 0 enablement of models. Candidates would develop a deeper understanding of the various ML models, and how they are executed, identify performance bottlenecks and enable faster development. Preferred Experience Minimum 10 years of relevant work experience. Strong background in C++ based development and debug, dealing with multi-threaded infrastructure and performance optimization Experience in creating cycle accurate modeling of IPs in C++ or SystemC / TLM. Understanding of SoCs, and bringing up of software stack from driver to application on simulation model. Understanding hardware metrics like latency/throughput on any sub-system, and what changes impact those metrics. Experience in software development environment on both Linux and Windows is required. Experience in technologies like Virtual Platforms, SystemC/QEMU models, Emulation platforms, Hw/Sw co-design, and Performance analysis is desired. Familiarity with hardware languages like VHDL, Verilog and System Verilog for simulation using tools like Modelsim, VCS, Questa Sim is highly desired. Academic Credentials Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Greetings from Tamilnadu Advanced Technical Training Institute (TATTI)! We are looking for an experienced Verilog and VHDL Trainer to deliver practical and conceptual training in digital system design. The role involves guiding learners through hands-on sessions using industry-relevant tools, preparing them for roles in the semiconductor and embedded systems domain. Job Type: Freelance Location: Chennai Key Responsibilities: Conduct training sessions on Verilog and VHDL Develop course materials, lab exercises, and projects Mentor learners and support project development Stay updated with trends in FPGA, ASIC design, and EDA tools Requirements: Proficiency in Verilog and VHDL Experience with tools like ModelSim, Vivado, Quartus etc. Strong communication and presentation skills Prior teaching/training experience is a plus Why Join TATTI? Work with a renowned technical training institute with over 40 years of experience . Collaborate with leading corporate clients . Enjoy career growth and continuous learning opportunities. Be part of an innovative and dynamic team . Apply Now: Interested, Click the link to apply!

Job Details Job Description: Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, discussions with customers, design reviews Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation Define, create and maintain all project related documentation, especially design documents with detailed analysis reports Provide support to customer during integration phases at test sites and support to production teams Qualifications Qualification Required: Bachelor's or Master's degree in Computer Science, Engineering in Electronics or Electrical or Telecom or VLSI Engineering or equivalent practical experience Requires minimum of 5+ years of experience in FPGA designs all the way from requirements to micro-architecture to implementation to debug and bringup on Hardware Preferred to have system level understanding Proficiency with System Verilog and RTL coding skills, timing closure, or STA, targeting high performance designs Very good understanding of latest protocol specifications for memory, bus protocol specification like AXI, PCIe and Ethernet interfaces, Security IPs (for ex: MACSec) Experience with FPGA tools and timing closure Hardware power-on and debug New product release and rollout support Customer technical support Good communication and presentation skills. Required Technical And Professional Expertise FPGA Design : Verilog/System Verilog RTL Coding FPGA Synthesis & Place&Router/Fitter Tools Functional Simulation Hardware Design : Logic Design & Debugging expertise Version control tools like Git Experience with scripting languages (Python, Perl, TCL, Bash, etc.) Job Type Regular Shift Shift 1 (India) Primary Location: Ecospace 1 Additional Locations: Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception(data collection), comprehension(data processing), and prediction (analytics). This holistic approach empowers Digantara to monitor all Resident Space Objects(RSOs) in orbit, fostering comprehensive domain awareness. Digantara seeks a highly skilled Senior Embedded Software Engineer to design and develop embedded software solutions tailored specifically for real-time image processing. You will leverage your expertise to enable the development of state-of-the-art embedded software with applications such as tracking objects from both space and the Us ? Be part of a collaborative and innovative environment where your ideas and skills make a real difference to the entire space realm. Push the boundaries with hands-on experience, greater responsibilities, and rapid career advancement. Competitive incentives, galvanizing workspace, blazing teampretty much everything you have heard about a : Design, develop, and implement embedded software for real-time image processing for satellite payload applications. Translate and optimize image processing algorithms to FPGA/SoC platforms to achieve low latency and high throughput. Collaborate with system-level designers and hardware designers, generate software functional requirements and architecture, and ensure seamless integration of software and hardware. Collaborate effectively with cross-functional teams to conceptualize, design, and implement optimal embedded software solutions for image processing. Define and implement interface and communication protocols for data handling between the satellite payload and bus systems. Develop clean, well-structured, maintainable code and execute comprehensive testing according to space industry standards (e.g., the ECSS software engineering standard). Implement rigorous software quality assurance practices, including static analysis, code coverage analysis, and other verification techniques. Develop efficient embedded software for high-performance embedded systems with the ARM Cortex processor architecture. Leverage AMD-Xilinx/Microchip EDA tools (e.g., Vivado/Vitis IDE, Libero SoC design suite) to develop efficient embedded software solutions. Troubleshoot and resolve embedded software defects and hardware interface Qualifications : B.Tech 5+ years of experience in Embedded software design and development, with a strong focus on image processing and experience in handling communication protocols. Strong proficiency in bare-metal and RTOS programming for embedded systems, with expertise in real-time scheduling, interrupt handling, and device drivers. Proven ability to optimize embedded software implementation, including code optimization, memory management, and power efficiency techniques. Proficiency in Embedded C and C/C++ programming languages. Strong understanding of data communication protocols such as I2C, UART, SPI, CAN, Gigabit Ethernet, LVDS, RS422, etc. Working knowledge of software configuration management tools and defect tracking Skills : Prior experience in embedded software implementation in the areas of satellite imaging payload or ground-based imaging systems is highly preferred. Working knowledge of FPGA/SoC-based embedded systems designed for image processing applications is highly valued. Experience in hardware-related programming of FPGA interfaces and high-level synthesis. Knowledge of implementing fault-tolerant embedded systems for satellite applications. Familiarity with digital image processing and implementation. Experience in Python programming language and knowledge of Verilog/VHDL. Experience with camera interfaces such as USB3, CoaXPress, CameraLink, PCIe, Gigabit ethernet, etc. General Requirements Ability to work in a mission-focused, operational environment. Ability to think critically and make independent decisions. Interpersonal skills to enable working in a diverse and dynamic team. Maintain a regular and predictable work schedule. Writing and delivering technical documents and briefings. Verbal and written communication skills as well as organizational skills. (ref:hirist.tech)

Job Summary We are looking for an experienced Senior RTL Design Engineer with a strong background in SoC architecture, logic design, and RTL development. This role is ideal for candidates who are passionate about software-driven digital hardware design and have in-depth knowledge of modern SoC systems, protocols, and low-power design Responsibilities : Design and implement scalable RTL architectures for complex SoC components using Verilog/SystemVerilog. Develop and maintain logic blocks aligned with architectural and functional specifications. Collaborate with design verification and architecture teams to define module interfaces and performance metrics. Implement low-power design techniques using software methodologies such as clock gating, power domain partitioning, etc. Model asynchronous interfaces and multi-clock domain logic for integration into larger SoC platforms. Analyze design performance and optimize RTL for area, power, and logical efficiency. Write clean, reusable, and synthesis-friendly RTL code following best practices and coding standards. Simulate and debug logic design using industry tools and waveform analysis. Integrate IPs and subsystems in a modular and maintainable way using software configuration and scripting Skills & Experience : 5+ years of experience in RTL design, logic development, and micro-architecture. Strong command over Verilog/SystemVerilog and digital design methodologies. Proven experience in designing software-driven SoC architectures with modular, configurable RTL. In-depth knowledge of AMBA protocols - AXI, AHB, APB. Experience in multi-clock domain logic and asynchronous interface design. Proficiency in low-power RTL techniques including power-aware coding and UPF/CPF flows (logic-level). Familiarity with RTL design tools such as Simulation (ModelSim/VCS), Linting, CDC/RDC tools. Scripting skills in TCL, Python, or Shell for automating RTL testbenches, configuration, or IP Qualifications : Bachelors or Masters degree in, Computer Engineering, or related field. Exposure to software-based SoC modeling or transaction-level modeling (TLM). Experience with design abstraction, reusable IP architecture, and configurable RTL components. Knowledge of interfaces such as USB, PCIe, SD/eMMC at RTL level. (ref:hirist.tech)

Sr Staff Engineer Design Verification [ Location: NOIDA] Job Description We are seeking a diligent Verification leader to join our team at leading semiconductor company. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities: Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers andmicroprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

In your new role you will:. Manage a Digital Verification Team working in R&D projects in a complex technical area. Resource pipeline balancing, allocate projects and co-ordinate the team. Building up and developing competencies and methodologies for IP/SoC Verification. Be the technical interface to internal development groups, project management and external development partners. Drive innovation in the form of new advancements (state-of-the-art verification methods, tool integration and flow automation). Envisage, implement, institutionalize and maintain the verification methods and infrastructure (e-g. automation to improve quality/efficiency in terms of cost and time). Accountable together with the PJM & CoC Head in meeting Quality, Cost, Deliverables, Represent your group in cross site methodology exchange. You are best equipped for this task if you have:. A degree in Electrical Engineering, Computer Science or similar technical field. At least 10 years of experience in the semiconductor industry inrelevant R&D departments and people management experience is must. Experience in Product Development, Digital Verification or Digital Design. Profound and proven problem-solving capabilities as well as strong communication skills to manage global and multi-cultural stakeholders and networks successfully. Good knowledge in your own technical area but a focus on management and coordination role. Excellent presentation skills which enable you to master the alignment across internal and external contacts in a multi-cultural environment. Highly motivated with ability to prioritize and perform under pressure. Proven ability to achieve results in a very dynamic and multi-site environment. Strong analytical and communication skills. #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener, Are you in?. We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon, Show more Show less

To work as a Frontend engineer and taking care of Synthesis, LEC, CLP and Power Analysis for complex SoC projects.. Job Description. In your new role you will:. Implement high-performance, low-power, and area-efficient digital designs.. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.. Optimize designs for power, performance, and area, and meet PPA goals.. Power analysis using PT-PX or equivalent flow.. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs.. Define and evaluate constraints and signoff Test/DFT mode timing requirements.. Your Profile. You are best equipped for this task if you have:. Strong fundamentals and experience in Synthesis and STA domains.. Write and implement block level and top-level timing constraints for Synthesis. Optimize designs for power, performance, and area, and meet design goals.. Knowledge on Power analysis and PT-PX flow.. Understanding of DFT flows, including scan insertion.. Write and evaluate Test/DFT mode timing constraints.. Thorough with Logic Equivalence Check debug capability.. Well known about UPF concepts and Low Power Checks at block and full chip level.. Defining and verification of STA constraint for Functional and Test/SCAN Modes.. Defining PVT’s corners required for covering all desired scenarios for a design. Knowledge on OCV/AOCV/POCV derates.. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.. VASTA timing closure based on chip IR drop.. Knowledge on signal SI analysis and PT-PX flow.. Contact:. swati.gupta@infineon.com. #WeAreIn for driving decarbonization and digitalization.. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.. Are you in?. We are on a journey to create the best Infineon for everyone.. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills.. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.. Click here for more information about Diversity & Inclusion at Infineon.. Show more Show less