FPGA Verification Lead

Role Overview: As a Lead FPGA Verification Engineer at NEC Mobile Network Excellence Center (NMEC) in Chennai, your primary responsibility will be to lead the RTL verification of FPGA-based designs from concept to tape-out. You will collaborate with design teams to comprehend architecture specifications and drive the development of robust verification environments utilizing SystemVerilog and UVM. Your pivotal role will ensure high-quality deliverables for Datacom or Aerospace applications. Key Responsibilities: - Lead and take ownership of the RTL verification of FPGA-based designs. - Define and execute FPGA verification plans and create testbenches using SystemVerilog/UVM. - Collaborate with design engineers to grasp architecture and micro-architecture specifications. - Conduct functional coverage analysis, regression testing, and troubleshoot failures. - Provide mentorship and guidance to junior verification engineers. Qualifications Required: - Bachelors or Masters degree in Engineering (BE/B.Tech/M.E/M.Tech or equivalent). - Minimum of 6 years of experience in FPGA verification. - Proficiency in FPGA platforms like Xilinx and Intel (Altera), including AXI-based design integration. - Strong expertise in verifying high-speed interfaces such as PCIe, DDR, and Ethernet. - Ability to develop verification IPs and conduct validation on FPGA platforms. - Proficient in SystemVerilog, UVM, and simulation tools like QuestaSim and VCS. - Solid understanding of HDL languages including Verilog, VHDL, and SystemVerilog. - Strong scripting skills in Perl, Tcl, or Python. - Experience in constructing self-checking verification environments with BFMs, checkers, monitors, and scoreboards. Note: No additional details about the company were specified in the job description.,