Senior ASIC RTL Designer

Eximietas Design

6 years

0 Lacs

hyderabad telangana india

Posted:1 week ago| Platform:

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Skills Required

design verilog systemverilog architecture power synthesis dft verification test planning debugging resolve timing support emulation prototyping

Work Mode

On-site

Job Type

Full Time

Job Description

Position: ASIC RTL Design Engineer

Location: Bangalore / Hyderabad

Experience: 6+ years

Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.
Create micro-architecture specs and ensure designs meet performance, power, and area targets.
Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness.
Collaborate with verification teams for test planning, debugging, and coverage closure.
Integrate IPs into top-level SoC and resolve timing and functionality issues.
Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.

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