2321 Verilog Jobs - Page 50

Institute of Information Science Postdoctoral Researcher 2 Person The Computer Systems Laboratory - Machine Learning Systems Team Focuses On Research Areas Including Parallel And Distributed Computing, Compilers, And Computer Architecture. We Aim To Leverage Computer System Technologies To Accelerate The Inference And Training Of Deep Learning Models And Develop Optimizations For Next-generation AI Models. Our Research Emphasizes The Following Job Description Unit Institute of Information Science JobTitle Postdoctoral Researcher 2 Person Work Content Research on Optimization of Deep Learning Model Inference and Training AI Model Compression and Optimization Model Compression Techniques (e.g., Pruning And Quantization) Reduce The Size And Computational Demands Of AI Models, Which Are Crucial For Resource-constrained Platforms Such As Embedded Systems And Memory-limited AI Accelerators. We Aim To Explore AI compiler: deployment methods for compressed models across servers, edge devices, and heterogeneous systems. High performance computing: efficient execution of compressed models on processors with advanced AI extensions, e.g., Intel AVX512, ARM SVE, RISC-V RVV, and tensor-level accelerations on GPUs and NPUs. AI Accelerator Design We aim to design AI accelerators for accelerating AI model inference, focusing on software and hardware co-design and co-optimization. Optimization of AI Model Inference in Heterogeneous Environments Computer Architectures Are Evolving Toward Heterogeneous Multi-processor Designs (e.g., CPUs + GPUs + AI Accelerators). Integrating Heterogeneous Processors To Execute Complex Models (e.g., Hybrid Models, Multi-models, And Multi-task Models) With High Computational Efficiency Poses a Critical Challenge. We Aim To Explore Efficient scheduling algorithms. Parallel algorithms for the three dimensions: data parallelism, model parallelism, and tensor parallelism. Qualifications Ph.D. degree in Computer Science, Computer Engineering, or Electrical Engineering Experience in parallel computing and parallel programming (CUDA or OpenCL, C/C++ programming) or hardware design (Verilog or HLS) Proficient in system and software development Candidates With The Following Experience Will Be Given Priority Experience in deep learning platforms, including PyTorch, TensorFlow, TVM, etc. Experience in high-performance computing or embedded systems. Experience in algorithm designs. Knowledge of compilers or computer architecture Working Environment Operating Hours 8:30AM-5:30PM Work Place Institute of Information Science, Academia Sinica Treatment According to Academia Sinica standards: Postdoctoral Researchers: NT$64,711-99,317/month. Benefits include: labor and healthcare insurance, and year-end bonuses. Reference Site 洪鼎詠網頁: http://www.iis.sinica.edu.tw/pages/dyhong/index_zh.html, 吳真貞網頁: http://www.iis.sinica.edu.tw/pages/wuj/index_zh.html Please Email Your CV (including Publications, Projects, And Work Experience), Transcripts (undergraduate And Above), And Any Other Materials That May Assist In The Review Process To The Following PIs Acceptance Method Contacts Dr. Ding-Yong Hong Contact Address Room 818, New IIS Building, Academia Sinica Contact Telephone 02-27883799 ext. 1818 Email dyhong@iis.sinica.edu.tw Required Documents Dr. Ding-Yong Hong: dyhong@iis.sinica.edu.tw Dr. Jan-Jan Wu: wuj@iis.sinica.edu.tw Precautions for application Date Publication Date 2025-01-20 Expiration Date 2025-12-31

We are looking for a skilled Regional Receivables Manager to join our team at Equitas Small Finance Bank. Roles and Responsibility Manage and oversee regional receivables operations to ensure timely recovery of outstanding amounts. Develop and implement strategies to improve collection efficiency and reduce delinquencies. Collaborate with internal stakeholders to resolve customer complaints and disputes. Analyze and report on key performance indicators to identify areas for improvement. Ensure compliance with regulatory requirements and company policies. Lead and motivate a team of collection professionals to achieve targets. Job Requirements Strong knowledge of Inclusive Banking, SBL, and Mortgages concepts. Excellent communication and interpersonal skills. Ability to work in a fast-paced environment and meet deadlines. Strong analytical and problem-solving skills. Experience in managing teams and leading by example. Familiarity with financial software and systems is desirable.

SoC NoC Verification Engineer - Lead India,Bangalore Full time Job Description SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM . Guide teams in debugging and resolving intricate design issues . Optimize performance, power, and coverage metrics . Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks .

FPGA Design Intern at PierSight | Jobs at PierSight As per industry standards December 15th, 2024 Role: FPGA Design Intern Industry Type: Space Technology Location: Ahmedabad Employment Type: Internship (6 months) Job Description: Are you ready to join the pioneering team at PierSight Space as a FPGA Design InternWere a Space-Tech company with teams in Ahmedabad, California and Bangalore on a mission to build the worlds largest constellation of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance. With backing from prestigious institutional investors like Alphawave Global, Elevation Capital, All in Capital, and Techstars, were set to make a significant impact. Key Responsibilities: 0-1 years of hands-on experience in implementing designs on FPGA Strong expertise in RTL coding of complex designs using VHDL/Verilog/SV Knowledge in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure Create well written block level design documentation Write testbench and sequences in SystemVerilog Familiarity with lab equipment Familiarity with interface protocols Knowledge of latest FPGA architectures Exposure to scripting languages Preferred Experience: Hands on experience with FPGA design suite Libero Tcl/perl/python scripting languages Good hardware and software debugging skills Knowledge on running quality checks such as CDC Knowledge on synthesis, static timing analysis concepts Knowledge on FPGA Hardware design is added advantage Benefits: Exposure to real-world projects and hands-on experience in Space technology Mentorship from experienced engineers in the field

Front-End Silicon Design & Integration (FEINT) Engineer The role: A Front-End Silicon Design and Integration (FEINT) Engineering role in our Security IP (SECIP) team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks, as well as support SOC integration of the IPs. The person: A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities: Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result) Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team Develop and adopt FEINT design and verification infrastructure, methodology and tools Preferred experience: BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc. Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix/Linux environment Familiar with RTL coding techniques for competitive PPA-measured QoR Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments Excellent communication skills (both written and oral) Self motivated, and committed to achievement Academic credentials: Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or possibly a related field Masters Degree preferred #LI-PS1 Benefits offered are described: AMD benefits at a glance .

Title: MTS Design Engineering - Memory Layout Design About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 12-15 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Title: MTS Design Engineering - Memory Layout Design About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Introduction: GlobalFoundries is looking for highly motivated Memory Design Engineer to work in the Memory IP group in the Global Organization, based in Bangalore. The successful candidate will work with 100% quality and minimal cycle time in mind. This role requires working closely with the internal design, layout teams, technology, test and product engineering teams. The roles and responsibilities will include the design, simulation and verification of custom memory design blocks like decoders, sense amplifiers, write drivers etc. Your Job: Circuit design, simulation, and characterization of full custom circuits Functional simulations and statistical analysis Sign off and release the memory IP s on dedicated IP validation test chips Support Silicon bring-up and characterization Participate in implementation & design/layout reviews Contribute with innovative ideas for addressing design problems Work closely and collaborate with IP design and layout teams Required Qualifications: Requires MTech in Electrical (VLSI, Microelectronics and related fields) from a reputed university with 12-15 years of relevant experience Applicant should have a proficient knowledge of and experience with EDA (Cadence, Mentor Graphics, Synopsys ) tools for schematic design & simulations (Virtuoso, Spectre, HSPICE, etc.) Experience in NVM Memory (MTPM/OTP/MRAM/SRAM/eFlash) designs Experience in timing characterization, Verilog is desirable General analog mixed-signal design concepts is desirable Circuit design, Reliability analysis, Statistical analysis of circuits Must have good technical verbal and written communication skills and ability to work with cross functional teams Be able to collaborate with technical design leads on multiple concurrent projects. Preferred Qualifications: Knowledge in various technologies (Bulk, CMOS & SOI) process is desirable Hands on knowledge of state-of-the-art memory or analog design flows Programming experience applicable to design flow automation tasks Dedication and the capability to work within a very dynamic interdisciplinary environment Knowledge of 45/32/28nm and below technology nodes is an advantage. Ability to communicate as well as work efficiently in an international multi-disciplinary environment. Exceptional Spoken and Written Proficiency in English Strong analytical and problem-solving skills. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

As a Logic Design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers. Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLL Additiona responsibiities: ogic (RTL) design, timing cosure, CDC anaysis etc. Understand and Design Power efficient ogic. Agie project panning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

We are seeking highy motivated individuas with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to hande the chaenging probems in future technoogies and designs. We are aso ooking for candidates with Strong C/C++background to ead our eading-edge agorithmswithin our EDA soutions to increase our design team’s productivity and chip quaity and performance. Our dynamic goba team is ooking to enist enthusiastic professionas to join word-cass hardware design teams responsibe for deveoping the most chaenging and compex systems in the word. We are seeking energetic, highy motivated individuas wiing to go the extra mie with the aim of heping the overa IBM deveopment team. Strong interpersona skis are needed to coordinate deiverabes and requirements from severa areas within and outside of the organization.There are many opportunities to gain and utiize a deep understanding of future issues and provide input towards decisions affecting system deveopment, ogica and physica design as we as sophisticated methodoogy directions. Individuas who are chosen to become a part of our word cass deveopment teams wi be heping advance IBM’s eadership in deveoping the highest performing computers and changing hardware soutions. Do you want to be an IBMerCome THINK with us! Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise 4+ years of IT experience Strong C/C++programming skis in a Unix/Linux environment is a must. VLSI knowedge, Knowedge in front end inting toos and checkers and RTL Checkers. Great scripting skis – Per / Python/She Proven probem-soving skis and the abiity to work in a team environment are a must Preferred technica and professiona experience RTL Lint Checkers , Front end verification fow, VLSI knowedge, VHDL/Veriog, computer architecture

As a Logic design Engineer in the IBM Systems division, you wi be responsibe for the microarchitecture design and deveopment of features to meet Secure, high performance & ow power targets of the Mainframe and / or POWER customers.Deep expertise in the impementation of functiona units within the core / cache / Memory controer / Interrupt / crypto / PCIE / DLLAdditiona responsibiities:ogic (RTL) design, timing cosure, CDC anaysis etc.Understand and Design Power efficient ogic.Agie project panning and execution.Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bacheor's Degree Preferred education Master's Degree Required technica and professiona expertise Minimum 8+ years of experience in Chip design and deveopment. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, mutipiers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Veriog

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: Are you an Analog Design Engineer with hands-on experience designing components like Bandgap references, High-Speed IO circuits, Low Dropout Regulators (LDOs), and Phase-Locked Loops (PLLs)? If you have a minimum of 2 years in the semiconductor industry, this role offers exciting challenges and opportunities to contribute to groundbreaking projects. Responsibilities: 1. Collaborate with multidisciplinary teams to ensure seamless integration of analog blocks into semiconductor products. 2. Design, simulate, and validate analog circuits, focusing on PLLs, LDOs, Bandgap references, and High-Speed IO circuits. 3. Perform detailed analysis, optimization, and troubleshooting to meet performance, efficiency, and reliability targets. 4. Stay informed about emerging trends and advancements in analog design and apply innovative solutions. 5. Develop and maintain comprehensive documentation to support design processes and product development. Requirements: 1. A Bachelors degree or higher in Electrical Engineering or a related field. 2. At least 2 years of experience in analog circuit design within the semiconductor industry. 3. Expertise in designing analog components such as Bandgap references, PLLs, LDOs, and High-Speed IO circuits. 4. Proficiency with industry-standard Electronic Design Automation (EDA) tools for design and simulation. 5. Strong analytical, troubleshooting, and problem-solving skills. 6. A solid understanding of semiconductor fabrication processes and technologies. 7. Excellent communication and collaboration skills. Preferred Qualifications: 1. Experience in mixed-signal circuit design and low-power techniques. 2. Familiarity with high-speed data communication interfaces. 3. Contributions to published research or patents in analog design. 4. A strong understanding of innovative methods to optimize performance and efficiency. Why Join Us? Work on industry-leading projects that make a global impact. Collaborate with a team of experts in a supportive and innovative work environment. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience, 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog, Experience developing and maintaining verification testbenches, test cases,and test environments, Preferred qualifications: Masters degree in Electrical Engineering, Computer Science, or equivalent practical experience, Experience with low power, debug, Gate Level Simulation (GLS), formal verification, Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs, Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders, About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration, Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology, Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios, Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools, Debug tests with design engineers to deliver functionally correct design blocks, Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs, Be the primary point of contact for functional verification of the IP for cross-functional teams, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form ,

Job Overview Our Systems Development team designs subsystems for various application segments, using the latest IP products from Arm and other vendors We are looking for a creative and enthusiastic SoC Design Engineer to join the team and help develop these systems As a SoC Design Engineer you will contribute to the specification, design and verification of various compute subsystems You will join a small team of dedicated engineers in Austin, as well as collaborate with multiple other groups inside of Arm to design our subsystem products, Would you love a wider exposure across multiple IP productsDo you want an opportunity to work globally with various internal teams to deliver systems optimized for performance and powerThen we want to speak with you! Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for subsystems, You'll work with the project team to understand and review the subsystem architecture, and develop the design specifications, verification team to review test plans, and help debug design issues as well as the performance analysis team to evaluate and improve subsystem performance, Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks You are going to contribute to developing and enhancing the design methodologies used by the team where they will guide and support other members of the team as needed to enable the successful completion of project activities plus balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills & Experience In addition to bringing your accomplishment of either Bachelors or Masters degree in Computer Science or Electrical/Computer Engineering or a similar related field and experience working in design of complex compute subsystems or SoCs, you will need Strong knowledge of digital hardware design and Verilog HDL, A detailed understanding and experience of the current design techniques for complex SoC development, Experience creating design specifications Good knowledge of logic development using Verilog Experience with Perl, Python or other scripting language "Nice to Have" Skills and Experience Experience with ARM-based designs and/or ARM System Architectures Experience with SystemVerilog and verification methodologies UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques PCIe subsystems for large SoCs and server applications In Return At Arm, we are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary These behaviors are assessed as part of the recruitment process Partner and customer focus Collaboration and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises We offer a hybrid approach to home and office working to provide an adaptable experience for all employees We expect some working time to be spent in office, to promote a strong collaborative environment with good team integration but are accommodating to different home working requirements, Salary Range $121,600-$164,600 per year We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm Salary is only one component of Arm's offering The total reward package will be shared with candidates during the recruitment and selection process, Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm, To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process, Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you, Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran,

Job Description As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency, Key Responsibilities RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies, Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance, Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups, Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance, Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility, Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions, Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics, Requirements Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL, Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable, Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus, Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation, Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment,

Job Description If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer Join us to be part of our journey in shaping the future of SoC design and innovation, Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs, You will work with the project team to understand and review the architecture, and develop the design specifications, Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks, You will work with the verification team to review test plans, and help debug design issues, You will work with the performance analysis team to evaluate and improve subsystem performance, You will also contribute to developing and enhancing the design methodologies used by the team, You will guide and support other members of the team as needed to enable the successful completion of project activities, You will balance other opportunities such as working with Project Management on activities, plans, and schedules Required Skills And Experience In addition to bringing your accomplishment of either Bachelors or Masters degree or equivalent experience in Computer Science or Electrical/Computer Engineering, Experience of 5+ years working in design of complex compute subsystems or SoCs, you will need Strong knowledge of digital hardware design and Verilog HDL! A thorough understanding and experience of the current design techniques for complex SoC development, Experience creating design specifications Experience developing RTL for SoC projects Experience with Perl, Python or other scripting language Desired Skills And Experience Experience with ARM-based designs and /or ARM System Architectures Experience integrating subsystems for PCIe, LPDDR, HBM, UCIe, Ethernet Experience with SystemVerilog and verification methodologies UVM/OVM/e Experience leading small teams or projects Experience or knowledge in the following areas Synthesis and timing analysis Static design checks, including CDC, RDC, X-Propagation, Linting Power management techniques DFT and physical implementation In Return At Arm, we are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary, Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm, To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process, Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you, Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran,

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We Make Real What Matters. This is your role! Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and improve these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will cooperate with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds We seek a graduate with an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute Phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. We value sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. Knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a phenomenal teammate, resilient and candid, Enjoy learning new things and build knowledge base in new area. We’ve got quite a lot to offer. How about you? This role is based in Noida but you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the world’s most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. Show more Show less

Job Summary: Seeking a Senior DFT Engineer with 10+ years of experience adept in SOC DFT implementation. Job Responsibilities Develop and implement DFT strategies for advanced VLSI designs. Collaborate with design and verification teams to ensure DFT requirements are met. Perform scan insertion, ATPG pattern generation, and BIST (Memory and Logic) implementation. Perform DFT simulations and analyze results to ensure test coverage and quality. Debug and resolve DFT-related issues throughout the design process. Stay updated on industry trends and advancements in DFT methodologies. Mentor junior engineers and provide technical guidance as needed. Job Qualification Senior DFT engineer with 10+ years of experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, LBIST. The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Must have worked on one SoC at least, from start to end. Must be proactive, collaborative and detail-oriented capable of exercising independent judgment Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug. The engineer with experience on debug and root cause the problem in simulation failures. BE/ME/B.Tech/M.Tech from reputed institutes Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve More information about NXP in India... Show more Show less

Hi All, Looking for DV - Verification Engineer with Pcie exp. Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols like PCie. Verification for complex IP’s and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol and Pcie. Please share your resume to jayalakshmi.r2@ust.com Regards, Jaya Show more Show less

Hi All, Looking for Design Verification Engineer with UVM and Verilog experience. Good understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IP’s and close the Verification to the challenging milestones. Strong knowledge of AXI4/AXI5 protocol Please forward your resume to jayalakshmi.r2@ust.com Regards, Jaya Show more Show less

Senior Verification Engineer Location: Bangalore/Hyderabad Experience: 5+ years 1Must have very good System Verilog/UVM experience Must have expertise in PCI gen6 and CXL3.1or Ethernet bus protocols Have experience in IP/SoC Verification Expertise in AMBA/AXI bus protocols and ARM CPU Experience in developing functional verification environments including the components like monitors, checkers, scoreboards and assertions Experience in code and functional coverage Scripting Language (PERL/Python/Shell/Makefile) Must have good debugging and problem-solving skills Good to have GLS verification experience Educational Qualification: BE/ME or BTech /MTech Show more Show less

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry’s toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs’ software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that’s one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance Job Description The position involves designing, developing and deploying UVM/C based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I3C, PWM. Responsibilities: Develop and track execution of chip level test planning to meet product requirements and established quality standards Lead a team to complete the pre-silicon verification of an SoC Execute and maintain chip level verification regressions. Triage and debug failing tests. Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification. Perform gate level verification across corners. Provide appropriate activity files for power analysis. Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure. Experience Level: 10-15 years in Industry Education Requirements: Bachelor or Master’s degree in Electrical and/or Computer Engineering Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture Strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage. Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Very strong Analytical debugging skills Knowledge on C Based Testcases. Knowledge of SoC,Memory and Cache Architectures Knowledge on Low power designs and architectures Verify and debug low-power design Debug SDF Back Annotated Gate Simulations Low-power implementation (UPF) Mixed Signal Real Number Modeling (RNM, Spice) Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

Role: FPGA Engineer Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus. Strong analytical and problem-solving skills, with the ability to optimize designs for performance, power, and resource utilization. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.

Key Responsibilities: Perform block- and chip-level functional verification of complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs and subsystems. Create and execute detailed verification test plans based on specifications. Develop constrained-random and directed test cases and debug simulation issues. Conduct functional and code coverage analysis and drive coverage closure. Use RAL (Register Abstraction Layer) for register-level testing. Develop and validate SystemVerilog Assertions (SVA). Candidate Requirements: • Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. • Experience: 6–10 years of relevant experience in ASIC/SoC design verification.

Title: Principal Engineer Design Enablement (GAN HEMT modeling) About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction: GlobalFoundries is seeking a motivated, self-driven engineer to develop Compact models of HEMT devices, which are actively used by clients to design state-of-the-art IC design solutions. Your Job : The role requires a strong background in semiconductor device physics. The candidate should be familiar with the electrical behaviors of semiconductor devices (DC/low frequency, RF/high frequency, noise, mismatch, etc.), and the types of test structures that are needed to characterize them. The candidate should be able to apply his/her knowledge of semiconductor device physics in a practical compact model extraction scenario, such as being able to analyze and explain the trends in the data, being able to distinguish real trends from noise , associate various physical phenomena with the observed trends, submit electrical characterization requests, extract various compact modeling parameters, do various QA checks and submit the model for release. The candidate should also be able to do design and layout of test structures; be able to correlate device cross section with layout; do various kinds of simulations in Cadence ADE; be proficient in writing python scripts for doing model parameter extraction, data analysis and QA; have knowledge of industry standard compact model families and parameter extraction tools/methodologies; have knowledge of Verilog-A and be able to write Verilog-A models; and be able to field customer queries pertaining the model. Other Responsibilities: Apart from strong technical skills, the candidate should also possess excellent communication skills and be able to work across geographies and time zones. He/She should be self driven and self motivated to excel, innovate and solve problems. This position is based out of Bangalore. Required Qualifications : PhD with specialization in HEMT devices Years of Experience 0 #NCGProgramIND