Serdes/PCIe IP Application Engineer

As a High Speed Serdes PHY Application Engineer, your role will involve the entire SOC design flow, including architecture, high speed Interface IP(IIP) integration, synthesis, design for test(DFT), low power design(UPF), CDC/RDC check, static timing analysis(STA), silicon test plan, silicon bring-up, and mass production silicon debug. In addition, you will: - Work closely with customers to understand new requests or customization features from customers PRD/MRD - Provide integration training to customers and conduct reviews on their major SoC milestones - Provide feedback to Synopsys R&D for customization features or continuous IIP product improvements - Participate in IIP design reviews to align development with future customer needs - Showcase creativity and innovation by developing small tools to simplify daily tasks or improve efficiency, and by authoring application notes for gate-level simulation, silicon debug, and physical implementation Key qualifications: - Bachelors and/or masters degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science - Minimum 10 years of IP and/or ASIC Design/Verification/Applications experience is required - Hands-on experience on RTL coding in Verilog, simulation, synthesis, static timing check, equivalence check, etc. - Domain knowledge in PCI Express, CXL, Ethernet protocols - Creative, results-oriented with the ability to manage multiple tasks concurrently - Good verbal and written communication skills in English and ability to interact with customers - High degree of self-motivation and personal responsibility - Good inference, reasoning and problem-solving skills, and attention to details Preferred Experience: - Synthesis, CDC, RDC, Lint, DFT, STA - ASIC/SoC tape-out from concept to full production - Scripting languages (Tcl, Perl, Python, Excel VBA, etc.) - Silicon debug and FPGA/hardware troubleshooting skills - Package, PCB design, SI/PI knowledge will be a plus,