2321 Verilog Jobs - Page 49

We are looking for Senior SOC Verification Engineers for Hyderabad & Bangalore location. 1) SOC Verification 2) SV UVM 4) C & Verilog Language Interested candidates, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com

Principal DFT Engineer (MBIST) in Pune, MH, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Principal DFT Engineer (MBIST) in Bangalore, KA, India Description Invent the future with us. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. About the role: The ideal candidate will work with multi-functional global teams to design, implement and verify Boundary Scan, ATPG (Stuck-AT/AT-Speed) SCAN, MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products. Will work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. What youll achieve: DFT features like EDT, SSN, shared bus based MBIST insertion, ijtag, simulation and debug on RTL and gates netlist Boundary Scan insertion, simulation and verification Scan insertion, Scan compression, Stuck-At, At-Speed test and coverage analysis Scan ATPG pattern generation, simulation and debug on RTL and gates netlist Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor, Cadence, Synopsys) STA DFT Test mode timing constraint development and analysis In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data Bachelors degree & 8 years of related experience or Masters degree & 6 years of related experience Expert with methods and techniques to design, implement and verify regular and shared bus based Memory BIST on repairable and non-repairable memories using Electrical fuses. Expert knowledge and practical work experience partnering with designers to implement highly customized and tools-driven MBIST solutions. Solid understanding of MBIST algorithms needed for 5nm and lower technology nodes and ability to code new algorithms, operation sets supporting tool driven solutions. Experience in implementing EDT, SSN, boundary scan, jtag/ijtag features. Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level Hands on experience in the usage of industry standard tools, like Siemens Tessent Shell flow, or Synopsys SMS/SHS flow Expert understanding tradeoffs to optimize coverage and test time reduction with the ability to foresee physical implementation and timing challenges during early development. Experience in working with physical design teams to support STA constraints, reviewing timing reports. Expert in using silicon debug/diagnosis tools to root cause silicon bringup and production test issue. Experience in setting up and running Scan DRC flows in RTL. Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl. Experience in revision control systems like GIT, perforce etc.. Needs in depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and identifying solutions to improve test coverage Experience in leading the effort to derive cell aware fault models and develop necessary flows to generate ATPG and to support silicon debug. Good knowledge of functional safety, clock domain crossing analysis, logic synthesis and scan insertion At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.

Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride-hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider-only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states.. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.. In this hybrid role, you will report to an ASIC Design Manager.. You Will. Manage a new team of engineers developing advanced silicon for our self-driving cars. Grow the team by hiring top talent at our new site in Bangalore. Hands on technical leadership and contributions to architecture, design, and verification of IP blocks. Work and coordinate cross-functionally with our U.S. and Taiwan silicon and partner teams. Develop methodologies and best practices to ensure on-time, high performance, and high-quality silicon. You Have. 6+ years experience managing ASIC or SoC development teams. Strong technical experience with the full digital design and verification cycle -from spec through bring-up. 5+ years of industry experience with high performance digital design in Verilog/SystemVerilog. Experience prioritizing resources across multiple projects on tight timelines. We Prefer. Industry experience with constrained random verification and UVM. Fluency in at least one high level programming language such as Python, C++. Experience with performance and power validation, and formal verification. Experience with prototyping systems on FPGA platforms or emulators. Experience with automotive silicon and standards. The expected base salary range for this full-time position is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements.. Salary Range. ?8,400,000—?10,200,000 INR. Show more Show less

Expected compensation: 30.00 USD Per Hour. HireArt is helping a global leader in AI development hire AI Quality Control Coding Specialists to train AI models to become proficient coders and help build the next generation of coding tools!. We are looking for experienced programmers, coders, and software engineers who are great at solving coding challenges (e.g., Codeforces, Sphere Online Judge, Leetcode) to train generative artificial intelligence models.. As an AI Quality Control Coding Specialist, your responsibilities may include:. Evaluating the quality of AI-generated code, including human-readable summaries of your rationale.. Solve coding problems by writing functional and efficient code.. Writing robust test cases to confirm code works efficiently and effectively.. Requirements. 3+ years of experience in a software engineering/software development role. Proficiency working with two or more of the the following languages:. Primary: Rust, Go, Verilog, Java Script, React. Secondary: Python C/C++. Complete fluency in the English language. Ability to articulate complex scientific concepts in a clear and engaging manner. Excellent attention to detail and ability to maintain consistency in writing. Solid understanding of grammar, punctuation, and style guidelines. Preferred Qualifications. Bachelor's and/or Master’s degree in Computer Science. Proficiency working with one or more of the following (in addition to the languages above):. SQL, Swift, Ruby, Rust, Go, NET, Matlab, PHP, HTML, DART, R, Apex, and Shell, C, or C#. Proven analytical skills with an ability to approach problems creatively. Adept communication skills, especially when it comes to understanding and discussing project requirements. A commitment to continuous learning, staying updated with the latest in coding advancements and best practices. Enthusiasm for teaching AI models and experience with technical writing. No previous experience with AI is necessary You will receive detailed instructions on the project if you meet the project requirements. Commitment: This is a full-time, independent contract position staffed via HireArt. This role is available for candidates who are currently based in India. Note: HireArt is the employer of record.. HireArt values diversity and is an Equal Opportunity Employer. We are interested in every qualified candidate who is eligible to work in the United States. Unfortunately, we are not able to sponsor visas or employ corp-to-corp.. Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Mandatory Skills 4+years Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash Proficiency in Unix environment.

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog.. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.. Experience in performance and latency architecture for an Anycast Redirector Maglev (ARM) based SOC.. Experience in mobile SOC performance model development, performance analysis, and workload characterization.. Experience performance measurement and debugging in an emulation environment.. Preferred qualifications:. Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.. Experience in low-power design verification.. Experience in microarchitecture innovation.. Knowledge of CPU, GPU benchmark characterization.. Knowledge in system software components, such as Linux, drivers, and runtime.. Knowledge of performance analysis tools.. About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.. Responsibilities. Develop simulators and architectural models of Google's Tensor System on a Chip (SOC).. Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements.. Participate in architectural and design evaluation of Tensor SOC features studies.. Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements.. Communicate analysis results qualitatively and quantitatively.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in architecture, hardware, digital design, and software co-design. 3 years of experience in Verilog/SystemVerilog.. Experience in computer architecture and digital design or Internet Protocol (IP) integration (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory).. Preferred qualifications:. Master's degree in Electrical Engineering, Computer Science, or a related field.. 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) (e.g., Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR) memory, Gigabit Ethernet, Flash).. Experience in developing architectures for Machine Learning Accelerators.. Experience in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, waveform debug skills with knowledge of chip design flows.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will integrate hardware and software stacks and operate them on emulation platforms for pre-silicon validation of our Google Cloud Tensor Processing Unit (TPU) projects. You will create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. You will be responsible for silicon bring-up, validation, characterization and qualification, and sustaining programs and their quality. You will help ensure our fleet runs at maximum efficiency, and help debug and root when causing issues. You will collaborate with Product Firmware, System Software and Application-Specific Integrated Circuit (ASIC) Design in the development of tools, validation firmware, functional and performance tests, and testing infrastructure for our platforms and Google Cloud data center systems.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Enable bring-up of chip features through firmware and driver stack. Integrate and validate hardware and software designs in pre-silicon.. Architect and design Application-Specific Integrated Circuit (ASIC) models for Emulation/Field Programmable Gate Array (FPGA) Prototypes. Design Register-Transfer Level (RTL) transformations to optimize mapping to Emulation/FPGA platforms and design solutions to improve Internet Protocol (IP) modeling.. Design solutions to improve hardware modeling accuracy and scale to various system configurations and enable serving of ASIC models for software and validation teams.. Bringup chip features on software reference models and hardware prototypes (e.g., Emulation/FPGA) and drive debug discussions with design/design validation/physical design/software/architecture teams and help root-cause failures.. Develop the integration plan with software and system partners, coordinate hardware and software delivery and benchmark performance.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Job Description. As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies. You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency.. Key Responsibilities. RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies.. Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance.. Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups.. Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance.. Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility.. Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions.. Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics.. Requirements. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL.. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable.. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus.. Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation.. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.. Show more Show less

Join our team and unlock your potential in the world of Semiconductor. We are looking for #TrainedFresher and. #internship in #analogLayout. Preferred Qualifications:. Knowledge of SiGe and CMOS technology nodes 45/32/28nm and below is an advantage. Hands-on knowledge of state-of-the-art analog design flows and knowledge of ADC, DACs is a plus. Good publication and patent record. Dedication and the ability to work within a very dynamic interdisciplinary environment. Ability to communicate as well as work efficiently in an international multi-disciplinary environment.. Exceptional spoken and written Proficiency in English. Strong analytical and problem-solving skills.. Percentage : min 70%,. internship completed engineers with hands on exp on layout will be preferred. #Intern and #trained candidates only considerable.. Explore exciting career opportunities at www.Digicommsemi.com. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.. AMD together we advance_. PMTS SILICON DESIGN ENGINEER. As a SerDes Verification Architect, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.. Key Responsibilities. Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).. Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.. Experience:. 16+ years of experience in SerDes verification or high-speed communication verification.. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.. Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.. Skills:. Solid understanding of SerDes architectures, link training, and equalization.. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).. Familiarity with hardware description languages (HDL) like VHDL or Verilog.. Strong analytical, problem-solving, and communication skills.. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.. Preferred Skills. Experience with Python, Perl, or similar scripting languages for automation.. Exposure to high-speed memory interface design and verification, including DDR controller IP verification.. Functional coverage, assertions knowledge in SV/UVM.. Ability to work in a fast-paced environment and manage multiple verification tasks.. Strong team player with good interpersonal and communication skills.. Benefits offered are described: AMD benefits at a glance.. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.. Show more Show less

Date 29 May 2025 Location: Bangalore, KA, IN Company Alstom At Alstom, we understand transport networks and what moves people. From high-speed trains, metros, monorails, and trams, to turnkey systems, services, infrastructure, signalling and digital mobility, we offer our diverse customers the broadest portfolio in the industry. Every day, 80,000 colleagues lead the way to greener and smarter mobility worldwide, connecting cities as we reduce carbon and replace cars. Could you be the full-time Studio Engineer in our Advanced & Creative Design Global (A&CD) team were looking for Studio Engineer is responsible to build a crucial relationship between A&CD Design Vertical and Engineering counterparts for better Integration of Exterior and Interior Components, Engineering Parameters, while also be equally involved for Data Preparation work on Visualization Activities. Organization VerticalAdvanced & Creative Design Global (A&CD) Reports directly toDigital Design Team Leader - A&CD Asia Studio collaborationDigital Design, Mobility Design, Visualization Design and CMF Design Teams InternalA&CD Team, RSC engineering organization (TD, COE, TSS, R&D), Procurement, Intellectual properties Organization. ExternalDesign Organizations, Design Agencies and Data Management Partners. Eligibility & Work Experience Bachelors or masters program in Mechanical Engineering, Automobile Engineering or related streams With a minimum professional experience of 2 years or more in handling Studio Engineering Responsibilities. Drive and Passion for sustainable future / mobility ecosystem and related solutions. Excellent level / Mastery on Digital Design tools (Alias, Catia, VRED). Workload Management Experience with strong skills in Microsoft Office Tools (PowerPoint, Excel) + Data Presentation Techniques. Professional experience of Production Design, DFQ, DFM, DPQ Processes. Good Interpersonal and Communication skills with internal and external stakeholders. Understanding of Mobility Design and Production Processes. Knowledge of industrial environment and associated technical and economic issues. Flexibility, ability to work on multiple projects with varied workscope. Experience of ensuring design deliverables that meet required quality standards. A portfolio / work samples demonstrating Studio Engineering Experience is essential to apply for this position. Ability to work independently and as part of a team. DesirablePrior Experience in Automobile, Mobility or Rail / Transportation Industry. Role & Responsibility Be the Key link between Design Vertical and Engineering counterparts for better Integration of Exterior and Interior Components. Build strong understanding of Engineering Parameters, Regulatory Specifications and Global Standards related to Rail Industry. Support A&CD -Mobility Design Team, Visualization Design Team and CMF Design Team in delivering Advanced Creative Design (A&CD) objectives. Data Preparation - for Visualization Design Team with regards to improved workflow from Design, Engineering and Final Visualization Deliveries / Renderings. Create Studio Engineering solutions that are compliant with applicable technical, contractual, legal and standards requirements. Timely delivery of A&CD deliverables to achieve Design Reviews / Project milestones. Ensure the consistency of the data deliveries for Internal & External Schedules. Improve relations and information exchanges with related projects teams. Promote the Importance of A&CD Design Vertical to all stakeholders inside and outside of the organization. Be able to organize and plan workload according to Tenders and Projects in progress. Manage workhours and timelines in accordance with the project budget. Ensuring the archival of completed projects and managing ongoing project / resource files on secured Database. Collaborate with the team to develop design proposals and ensure timely and efficient delivery. Stay up-to-date and introduce newer AI tools and integration techniques and keep innovating design approaches and methods. Fluent English communication is essential for the Role. Contribute to an engaging, collaborative and a thriving studio culture. Competencies (Proficiency progressionfrom A being the lowest to E being the highest level.) Developing Oneself - D Communication -D Drive for Results -E Building Partnerships -E Developing Others - B Initiative -D Team Leadership - B Strategic Outlook -E Technical skills (Proficiency progressionfrom A being the lowest to E being the highest level.) Determining and Managing Stakeholder -E Modelling and Simulation-E Concept Generation -D Systems Integration and Verification -E Integration of Design Deliveries -E You dont need to be a train enthusiast to thrive with us. We guarantee that when you step onto one of our trains with your friends or family, youll be proud. If youre up for the challenge, wed love to hear from you! As a global business, were an equal-opportunity employer that celebrates diversity across the 63 countries we operate in. Were committed to creating an inclusive workplace for everyone .

We are seeking highly skilled and motivated System-on-Chip (SoC) Emulation engineers to join our diverse team at Arm! Our team focuses on performance architecture and PnP analysis of Arm SoCs/SoPs (System-on-Package), System level infrastructure (SoC/SoP/Rackscale/Podscale) in pre- and post- silicon environments. Working closely with implementation teams and customers, we'develop best-in-class silicon platforms across markets such as servers, accelerators, client, infrastructure, IoT, and automotive. Responsibilities: Supporting multiple Emulation environments using the latest emulation techniques. Building early SoC platforms to facilitate performance/power analysis and debug. Able to handle/modify RTL and stitch together SoCs with standardized interfaces from scratch for bare-metal and validation OS based bringups. Collaboration with design teams to ensure the production of clean RTL code. Developing system level testbenches to implement performance and power benchmarks, simpoints and use cases in emulation platform. Integrate observation options to assemble and debug performance/power studies, correlate with pre-Si simulation/post-Si, lead larger implementation teams for emulation at later implementation phases and work with post-Si teams for analysis/tuning. Help drive innovation in model building and debugging methodologies. Collaborate with SoC Architecture team to create testplans covering all metrics for the product. Define flexible/reduced SoC configurations allowing reduction in simulation and emulation capacities, while providing accurate performance estimates. Collaborate with emulation vendors to define distributed systems to split huge SOC netlist between multiple emulation boxes. Required Skills and Experience : Experience (3-6 years) in SoC Performance verification and emulation environment bringup in the semiconductor industry. A background in Electrical Engineering, Computer Engineering, or Computer Science with an expertise in computer architecture and microarchitecture. Proficient in RTL (SystemVerilog, Verilog, VHDL), C/C++ for bare metal code, system validation using OS, test code development, strong scripting capabilities, particularly in Python, TCL, and shell scripting. Excellent communication, and interpersonal skills with ability to convey complicated solutions. Drive early and detailed performance/power analysis as an expert Emulation Architect at Arm, focusing on diverse silicon platforms Preferred experience: Experience in developing, building, and releasing large multi-billion gate hardware emulation models. In-depth knowledge of key hardware emulation vendor solutions for emulation and prototyping. Experience working with design and software teams on design verification tests, PPA workloads, and software workloads

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. At Arm, our work goes beyond multiple divisions where we'drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

As an Implementation Engineer in Arms Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible. Responsibilities: Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results. Required Skills and Experience : Bachelors or masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively. Possess a high level of dedicated, initiative and problem-solving skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2. Proven programming and scripting skills eg. Tcl, Perl, R, Make, sh. Nice To Have Skills and Experience : Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Job Description Candidate should have working experience with AMS Verification on multiple SOC s or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as we'll as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of A DCs and DACs , current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Your Profile Bachelors with 5+ years or Masters with2+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams , SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position: 6+y, 1 position: 4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash... Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE Other Languages English: B2 Upper Intermediate Seniority Regular Hyderabad, IN, India Req. VR-115262 Manual Testing Automotive Industry 20/06/2025 Req. VR-115262

Looking for Siemens EDA ambassadors: Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We Make Real What Matters. This is your role. Questa verification IP’s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don’t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 4-7 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #DVT

Key Skills: Architect, System Verilog, Verilog, PCI Roles and Responsibilities: Architecture Design: Develop and optimize PCIe architectures for high-performance SoC designs, including switches, interconnects, and communication protocols. Protocol Expertise: Design and implement PCIe solutions that support various communication protocols such as PCIe, CXL, and AMBA/AXI. System Understanding: Contribute to overall SoC design by ensuring seamless communication between various IP blocks and subsystems. Performance Analysis: Conduct detailed performance analysis and benchmarking of PCIe designs to identify bottlenecks and improvement areas. Collaboration: Work closely with hardware, software, and verification teams to meet system and performance requirements. Troubleshooting: Identify and resolve complex PCIe design and simulation issues. Research and Development: Stay updated on PCIe specifications; contribute to new standards, methodologies, and tools. Engage in research projects to explore new PCIe programs and protocols. Skills Required: Primary Skills: Proficient in PCIe design and optimization techniques Strong understanding of digital design principles and SoC architecture Experience with Verilog and SystemVerilog Knowledge of RTL simulation tools and verification environments (e.g., Cadence, Synopsys, UVM) Expertise in PCIe, CXL, and AMBA/AXI protocols Soft Skills: Excellent problem-solving and analytical abilities Strong communication and collaboration skills Ability to work independently and within a team High attention to detail and quality focus Passion for research and innovation Preferred Skills: Experience with PCIe Gen-4/5/6 protocols Knowledge of ASIC design flows Familiarity with scripting languages (e.g., Python, Perl) Experience with version control systems (e.g., DesignSync, Git) Background in PCIe architecture, SerDes concepts, and low-power design Experience with synthesis tools (DC/DC-NXT, Fusion Compiler) Understanding of synthesis constraints and timing (STA) Experience with Spyglass (Lint, DFT, PM, CLK/RST, CDC/RDC) Formal verification using tools like Formality or Conformal LEC Publication history in technical journals or IEEE conferences is a plus Education: Bachelor's or Master's degree in Engineering or a related field

Key Skills: Asic Verification, System Verilog, Verilog, PCI, Ethernet Roles and Responsibilities: Verify a block or a functional feature and lead it to closure. Write and architect scalable and reusable testbenches from scratch, using the framework of the verification methodology. Create test cases, functional coverage models, and bring the verification to closure. Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Be involved in documenting the verification strategy including test plans, verification micro-architecture, coverage objects, etc. Participate in and own verification strategic decisions that will help in the long run. Skills Required: Deep understanding of the full ASIC cycle, from conceptualization to TapeOut. Strong experience writing and debugging test benches. Proficiency in constrained random verification methodologies like UVM, VMM, or OVM. Strong knowledge of SystemVerilog. Solid command over object-oriented programming (OOP) principles. Open to learning and applying innovative verification methodologies and strategies. Motivated, self-driven, and able to work independently. Education: Bachelor's or BE degree in Engineering.

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. DFT ATPG Engineer D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs . We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! Your Responsibilities Will Include: Partitioning for ATPG and hierarchical approaches. ATPG compression and serialization. RTL-Scan insertion and design rule fixing. STA constraints, Primetime execution, and timing exception flow. Interfacing with ASIC design teams to ensure DFT design rules and coverages are met. Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques. Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis. Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE. Having experience with state-of-the-art industry-standard DFT tools. Being hands-on from the "nitty gritty" details to high-level planning. Minimum Qualifications: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Location Bangalore, Karnataka, India Employment Type Full time Location Type Hybrid Department R&D - HW Silicon Engineering At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Bengaluru, Karnataka headquarters 3-5 days per week. The Role: DFT Engineer - MBIST D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader. Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team! What you will do: Your responsibilities will include: Defining Memory Built-In-Self-Test (MBIST) architecture and running MBIST logic insertion tools. Bringing up and writing constraints for register-transfer-level (RTL) test DRC tools. Enabling DFT RTL verification and designing tests to validate all DFT logic. Identifying and implementing any required RTL fixes. Running scan chain insertion flows and tools. Generating scan coverage figures and debugging any gaps. Delivering schedules and staging plans for DFT intercepts into overall product timelines. What you will bring: BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field. 5+ years of experience with DFT technologies, including scan test and MBIST. Experience with a hardware description language such as Verilog, System Verilog, or VHDL. Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.). Ability to work well in a diverse team environment. Experience delivering detailed technical documentation. Equal Opportunity Employment Policy d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day. d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.