Senior FPGA Validation Engineer

Role Overview: As an R&D - Validation Engineer (FPGA), your primary responsibilities will include FPGA design and porting ASIC RTL to FPGA, generating FPGA bitstreams and validating them on hardware. You will work with Linux environments to develop test/control scripts and have strong experience in FPGA design and validation. Additionally, you will be hands-on with Xilinx tools (Vivado, ISE) or Synopsys FPGA tools, proficient in Verilog/SystemVerilog, RTL design, and simulation. Your programming/scripting knowledge in C, C++, Python, Perl, and Tcl will be essential for this role. You will also perform debugging using lab equipment such as oscilloscopes, logic analyzers, and protocol analyzers. Key Responsibilities: - FPGA design and porting ASIC RTL to FPGA - Generation of FPGA bitstreams and validation on hardware - Working with Linux environments and developing test/control scripts - Having strong experience in FPGA design and validation - Being hands-on with Xilinx tools (Vivado, ISE) or Synopsys FPGA tools - Proficiency in Verilog/SystemVerilog, RTL design, and simulation - Utilizing programming/scripting knowledge in C, C++, Python, Perl, and Tcl - Performing debugging using lab equipment such as oscilloscopes, logic analyzers, protocol analyzers Qualifications Required: - 5+ years of experience in FPGA design and validation - Proficiency in Xilinx tools (Vivado, ISE) or Synopsys FPGA tools - Strong knowledge of Verilog/SystemVerilog, RTL design, and simulation - Programming/scripting skills in C, C++, Python, Perl, and Tcl - Experience in debugging using oscilloscopes, logic analyzers, protocol analyzers,