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You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will conduct coverage analysis to ensure the validation's completeness, implement assertion-based verification to guarantee functional robustness, and collaborate across teams to align design and verification milestones. Your tasks will also involve working with RAL to validate register-level behaviors, creating testbenches for simulation, and optimizing performance efficiency. If you have 6 to 10 years of relevant experience and are eager to make a significant impact in chip-level verification, we encourage you to apply for this permanent position. This is a Work from Office opportunity located in Siruseri, Chennai. Immediate joiners are preferred. Don't miss this chance to be part of a dynamic team and contribute to cutting-edge chip design projects. Send your resume to Venkatesh@coventine.com or contact us directly to explore this exciting career opportunity. Join us in shaping the future of hardware design and advancing your career in the field of design verification. #Hiring #DesignVerification #SystemVerilog #UVM #ChipDesign #ASICVerification #VerificationEngineer #ChennaiJobs #HardwareDesign #CareerGrowth #Recruitment,