9 Assertionbased Verification Jobs

As a Senior Design Verification Engineer, you will be responsible for technically leading a team of verification engineers on Sub-System Verification. This includes architecting the testbench and developing in UVM or Formal based verification approaches, defining test plans and tests for block level verification, collaborating with the design team on test plans, closure of code, and functional coverage, partnering with analog co-sim and software team in enabling top-level chip verification aspects, developing end-to-end scenarios, bringing up GLS setup, and driving issues faced in the same to closure. You will also support post-silicon verification activities while working with other enginee...

As a Verification Engineering Manager, you will be responsible for leading and managing a team of verification engineers. Your role will involve providing guidance, mentorship, and performance feedback to ensure the team's success. Additionally, you will ensure the definition and implementation of test and verification plans to meet project goals and requirements. Collaboration with design, architecture, and cross-functional teams is crucial to ensure alignment and thorough verification. Your expertise will be key in identifying and resolving verification issues and bugs to ensure timely project delivery. Key Responsibilities: - Lead and manage a team of verification engineers, providing gui...

As a project management specialist at Truechip, you will oversee all aspects of multiple projects to ensure they meet goals on time and with high quality. Your responsibilities will include organizing people, tasks, and resources to bring about successful conclusions. Leading multiple project management team members and projects directly will be a key part of your role. Truechip is seeking a leader who can transform project teams with a Go-Getter attitude and deep understanding of team strengths and customer needs. You will not only manage projects but also serve as a role model for your team members. Additionally, direct interaction with multiple customers and reporting to the CEO will be p...

Job Description: As a Digital DV Engineer at the company, you will be responsible for developing and maintaining reusable, scalable, and modular processor-level verification environments using UVM System Verilog. Your role involves designing and implementing test plans, testbenches, and directed/random tests to validate ARM M-series and RISC-V processor designs, with exposure to DSP processors considered a plus. You will integrate and verify processor subsystems in SoC environments, ensuring seamless interaction with other components. Tasks will include executing regression tests across various scenarios and corner cases to ensure functionality and robustness. Key Responsibilities: - Design ...

As a Processor Verification Engineer at our company, you will have a fantastic opportunity to contribute to state-of-the-art processor verification projects. If you have a passion for verification, deep expertise in ARM M-series and RISC-V processors, and the skills to execute complex SoC verification tasks, we encourage you to apply. **Key Responsibilities:** - Develop and maintain reusable, scalable, and modular processor-level verification environments using UVM System Verilog. - Design and implement test plans, testbenches, and directed/random tests to validate ARM M-series (Cortex M33, M85, M55, M4, M0, etc) and RISC-V processor designs. Exposure to DSP processor would be a plus. - Inte...

As a Verification Engineering Manager, you will lead and manage a team of verification engineers, providing guidance, mentorship, and performance feedback. You will ensure the definition and implementation of test and verification plans, collaborating with design, architecture, and other cross-functional teams to ensure alignment on project goals and requirements. Monitoring and analyzing coverage reports will be crucial to ensure thorough verification, and you will be responsible for identifying and resolving verification issues and bugs to ensure timely project delivery. Continuously improving verification processes, methodologies, and tools will also be a key part of your role. Managing p...

As a successful candidate for this role, you should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. You should have at least 10 years of experience in Camera ISP image processing or other multimedia IPs like Display or Video Codec. Additionally, you should have a solid background with System Verilog Assertions (SVA), assertion-based verification, and formal verification, with at least 4 years of experience in people management and employee development. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Compute...

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer based in Siruseri, Chennai. In this role, you will have the opportunity to work closely with a top-tier client and play a pivotal role in developing next-gen chip-level verification environments utilizing System Verilog and UVM methodologies. This is a full-time position that requires you to work from the office. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. Your tasks will include developing verification test plans based on detailed design specifications, constructing UVM-based simulati...

You are invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai! In this role, you will have the opportunity to work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. As a Senior/Lead Design Verification Engineer, you will be responsible for functional verification at both block and chip levels for complex designs. You will play a crucial role in developing verification test plans based on detailed design specifications and constructing UVM-based simulation environments using System Verilog. Additionally, you will...