2321 Verilog Jobs - Page 35

Job Description: 4 to 12 years of experience mainly in design Experience in Verilog and/or System Verilog Working experience with AMD/Xilinx FPGA and Vivado Experience in Video domain (DisplayPort/MIPI) is preferred Location: Hyderabad

Responsibilities: * Collaborate with cross-functional teams on project requirements and deliverables. * Ensure compliance with IEC 60601 standards for medical devices. strong understanding of FPGA platforms AMD/Xilinx, Vivado, VHDL and RTL. Provident fund

RTL Verification Experience : 5+years Location : Hyderabad Job Description:Hardware Verification Engineer Basic Job Deliverable:HW Verification Engineer o Responsible for RTL verification, developing Develop SV/UVM testbenches at Top/Sub-system/Block-levels. o Responsible for driving test plan and test spec development and execution, generating documents, such as user-guide, test plan, test spec, test report etc., o Engaging in verification environment architecture and methodology development. o Experience:  Experience in System Verilog and UVM programing  Experience with verification of protocols like Ethernet/PCIe/SPI/I2C/USB  Experience in HW testing, including working with test equipment – logic and traffic analysers, test generators, etc. Experience with Xilinx technology and tools, FPGA verification and test  Strong debugging skills at device and board level  Scripting language experience like Perl, Python or TCL  Excellent interpersonal, written and verbal communication skills  Excellent communication, problem solving and analytical skills Interested,please drop your updated CV to janagaradha.n@acldigital.com

IP Verification Engineer Experience : 5-7 years Location : Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging. Basic Job Deliverable:Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera SV/UVM Functional verification Expertise in Vivado for simulation debugs Interested,please drop your CV to janagaradha.n@acldigital.com

Design and implement digital circuits using FPGA technology . Apply a solid understanding of digital logic design principles . Develop code using VHDL (preferred) and/or Verilog for FPGA applications. Use Vivado tool for synthesis, implementation, and debugging. Test and validate designs to ensure they meet performance specifications. Collaborate with cross-functional teams to align design with project goals. Analyze and resolve complex issues with strong problem-solving skills . Communicate effectively and contribute in a collaborative environment . Manage multiple projects with independence and accountability . Stay current with evolving FPGA tools and technologies .

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description We are seeking a diligent Verification leader to join our team at Renesas. The Verification engineer will be responsible for performing various verification tasks including Test Plan creation, Testcase creation, Coverage closure, Requirements traceability and Gate Level Simulation. They will also review system requirements and track quality assurance metrics. Ultimately, the role of the Verification Engineer is to ensure that our products, applications, and systems work correctly, safely & securely. Responsibilities Drive Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors. Work closely with system architects to understand high level specifications to be able to verify them. Work with various EDA vendors to deploy next generation tools Build strong collaboration with other R&D teams such as RTL, DFT, digital IP, PD, Design Enablement, Emulation, and Validation to achieve project milestones Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies Responsible for developing detailed Technical SoC verification execution plans, progress reports and tracking milestones, managing technical risks, and providing mitigations to meet schedule quality and costs commitments. Communicate across technical teas as well as provide executive level presentations Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs. Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI. Qualifications Degree in Electrical/Electronic Engineering, Computer Engineering or Computer Science At least 14 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits. Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC. Experience in Microcontroller and Microprocessor architecture & Interconnect Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR5/5x) and memory controllers. Advanced knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus High proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and constrained random methodologies. Good knowledge of formal verification methodologies and assertions. Experience with debugging of designs pre- and post-silicon, in simulation and on the bench. Excellent written and verbal communication skill. Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals. Fair domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, UCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

FPGA ENGINEERING INTERN Are you someone who is passionate about challenging the status quo? Do you enjoy the process of problem solving, a process where you recognize areas of improvement and iterate and innovate to improve? Does your curiosity and desire to learn drive you? If so, then join IMC as a Hardware Engineer Intern! At IMC, Hardware Engineers don t just write code and design technology. They are responsible for spotting new opportunities, developing new technologies and solving problems. As a result, they deliver results and make a difference. IMC knows that having the best technology is what drives our business. Hardware development here is innovative, pragmatic and fun, even as complexity grows. WHAT YOU LL DO: As a Hardware Engineer Intern, you will learn what it means to be an Engineer in a real-world environment. The internship program is focused on enhancing your knowledge of algorithm complexity, professional design, and writing fluent code. Your responsibility does not stop at programming; it also encompasses knowledge building of our business model and building relationships across our trading and technology teams. As a Hardware Engineer Intern at IMC you will be supported by both a mentor who will oversee your projects and professional development. You will have access to pair programming and code reviews, not to mention our incredible social activities and events. WHAT WE LOOK FOR: Student in (pen)ultimate year of Electrical Engineering or Computer Science Engineering Strong analytical skills and desire to solve complicated problems programmatically; Must have proficient experience in Verilog, VHDL or other RTL programming (additional software experience is a plus; Python, C++, or similar); Interest in financial markets is a must, but no prior knowledge or experience is required; Available for at least 9 weeks. OUR CULTURE: We are at the core a trading firm; however, we value trading and technology equally and we believe that cooperation between traders and technologists is one of our great strengths. This is also reflected in our organizational and remuneration policies. We believe in fostering a truly flat environment in which great ideas can be recognized as well as put into practice from anybody within our organization. Internship Stipend INR 25,00,000/- Per Intern for 2 Months [Including INR 5,00,000/- Sign on Bonus] IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we ve been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture, and our commitment to giving back. From entering dynamic new markets to embracing disruptive technologies, and from developing an innovative research environment to diversifying our trading strategies, we dare to continuously innovate and collaborate to succeed.

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning P REFERRED EXPERIENCE : Understanding of Design for Test methodologies and DFT verification experience ( eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc .) Experience with Mentor testkompress and/or Synopsys Tetramax /DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 10+Yrs of exp #LI-SR4

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your day will involve overseeing the application development process, coordinating with team members, and ensuring project milestones are met. Roles & Responsibilities:Bachelors degree in computer science, Electronics Engineering or related fields and 6+ years of related professional experience.Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of DesignsCore DFT skills considered crucial for this position should include some of the following Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debugUnderstanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax)Experience coding in Verilog RTL, and scripting language like TCL, and/or PerlProficient in Unix/Linux environmentsStrong fundamentals in Digital Circuit Design and Logic Design are required. Professional & Technical Skills: - Must To Have Skills: Proficiency in Design for Testability (DFT)- Strong understanding of software development methodologies- Experience in leading and managing software development projects- Knowledge of technologies and tools used in software development- Excellent communication and interpersonal skills Additional Information:- The candidate should have a minimum of 5 years of experience in Design for Testability (DFT)- This position is based at our Chennai office- A 15 years full time education is required Qualification 15 years full time education

Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required: Bachelors degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints

-6 years of professional experience in FPGA design, development, and verification. Proven track record of delivering FPGA-based projects from concept to production. Technical Skills : Proficiency in HDL languages ( VHDL and/or Verilog /SystemVerilog). Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, or Microchip Libero. Strong understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Familiarity with high-speed communication protocols (e.g., PCIe, Ethernet, USB, JESD204B). Experience with simulation tools (e.g., ModelSim, Questa, or VCS). Knowledge of scripting languages (e.g., Python, TCL, or Perl) for automation. Familiarity with embedded systems and hardware-software co-design is a plus. Soft Skills : Strong problem-solving and analytical skills. Ability to work independently and collaboratively in a team environment. Excellent communication skills for technical discussions and documentation. Preferred Qualifications : Experience in a regulated industry (e.g., aerospace, defence, or medical devices). Knowledge of digital signal processing (DSP) or high-speed digital design. Familiarity with SoC architectures (e.g., Xilinx Zynq , Intel Cyclone) and IP integration. Experience with version control tools (e.g., Git, SVN).

Job Title: RTL Design Engineers Exp Level: 4+ yrs Loctaion: Hyderabad /Bangalore Job Description: • RTL coding knowledge • Top-level (SOC) level basic industry standard Arch knowledge • SoC & IP level Integration knowledge • IPXACT knowledge • IORING and Phys & GPIOs basic functionality • Design Partitioning(Tilification) knowledge • Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge • Tools knowledge: Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC 0in Formality and conformal LEC tool • Design and scripting languages: Verilog and SV Perl Python TCL

Greetings from Evon Technologies Pvt. Ltd.! We are a team of 450+Technologists catering to our international clients for software services and consultation.We are a CMMI Level 3 company and Top Mobile App Development Co. of 2021. We currently have projects and teams working on iOS, Android, Java, HTML, PHP, Ruby on Rails, Phone Gap, .Net, Angular, Node, React, Salesforce, PowerBI and other trending technologies. We are expanding at a rapid rate and are looking for people who are smart, dedicated and will make an excellent addition to our existing teams. Currently, we are hiring FPGA/RTL Developers and are looking for Smart, pragmatic, self-driven IT professionals who are willing to learn and contribute towards organizational & personal growth. Location: Dehradun Looking Immediate candidates Experience Required : 3 + years SKILL SETS Required: - Minimum 3+ yrs Fair work experience on software development over FPGA Experience in physical layer signal processing Experience in Verilog/VHDL and working experience on Xilinx FPGA (vivado) Experience in DO-254 based development and documentation. Qualifications Design Engineering, Electrical Engineering, and Product Design skills Experience in Computer-Aided Design (CAD) Strong analytical and problem-solving skills Knowledge of FPGA and RTL design methodologies Bachelor's degree in Electrical Engineering, Computer Engineering, or related field Interested candidates can mail their resume to ethi.sharma@evontech.com

Looking for Siemens EDA ambassadors: PowerPro PV/CAE for Power Estimation /Optimization We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us - whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by increasing efficiency and customer happiness Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: Calypto System Design "Central Engineering Group (CEG)" group. CSD works on cutting edge tools like PowerPro, Catapult etc. The Product Validation and Customer Support team of CEG ensures quality products, educated and satisfied customers in the market for High Level Synthesis. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Work on different methodology for customer scenario. Provide script-based solution for quick turnaround time. Work on RTL to GDS flow , Glitch, Veloce PowerPro, PowerPro optimization flows. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, RTL to GDS flow expertise, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Strong Debugging Skills is must. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Knowledge of different tools like (DC, Fusion compiler, RTL Architect, Prime Power, Prime time, Zebu, joules, Gate sign off tools etc ) Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. We’ve got quite a lot to offer. How about you? We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday Accelerate transformation Hybrid

Requisition ID: 7969 Bangalore, India Enphase Energy is a global energy technology company and leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, Enphase transformed the solar industry with our revolutionary microinverter technology, which turns sunlight into a safe, reliable, resilient, and scalable source of energy to power our lives. Today, the Enphase Energy System helps people make, use, save, and sell their own power. Enphase is also one of the fastest growing and innovative clean energy companies in the world, with approximately 68 million products installed across more than 145 countries. We are building teams that are designing, developing, and manufacturing next-generation energy technologies and our work environment is fast-paced, fun and full of exciting new projects. If you are passionate about advancing a more sustainable future, this is the perfect time to join Enphase! About the role Enphase is looking for mid-level engineer with verification experience on Firmware (in C-language) for ARM Cortex M4 based ASICs to join our team in Bangalore India. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers. What you will do Work on creating verification plan based on the FW specification for Boot ROM Use the SOC RTL & Boot ROM image (i.e., derived from C-code) in system verilog based logic verification environment & complete the functional verification Define and execute verification activity for security aspect of the SOC (both for compliance & penetration threats verification) Generate coverage metrics, collaborate with FW developers on the correctness & completeness of Boot FW Be the single point contact for Boot Verification and enable the Tapeout for all control ASICs of Enphase Who you are and what you bring Fair understanding and experience of logic verification environment (UVM & System Verilog) Fair understanding of ARM microcontroller (Preference Cortex M4) architecture & debug infrastructure Hands on experience of C-code verification for ASICs Awareness of Device security aspects & potential threat modes will be a significant added advantage Awareness of Cryptography algorithms, data encryption/decryption verification will be a significant added advantage Ability to quickly adapt to other categories of C-based/System Verilog based IP verification Experience and ability to bring complex SOCs into the physical world and into production. #Logic Verification #Embedded C Verification #ARM #Boot. Prior hands on work experience of at least 6 years in Logic IP/DW Verification.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER The Role We are currently seeking a highly skilled verification engineer for GFX sub-system(Graphics Power Management) verification team. The Person A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Key Responsiblities Work with all partners such as lead architects and block design teams to understand features to be implemented and verified. Develop robugs test plan for both synthetic and real workload trace Debug verification test failures, working with the design teams Make sure the design meets functional/performance/power expectations Must have ASIC design knowledge and be able to debug Verilog RTL code using simulation/emulation tools and do test plan, test creation and triage, coverage, and assertion etc. Must demonstrate strong analytical thinking and problem-solving skills with an excellent attention to detail. Must have good English hearing, speaking, reading, and writing capabilities. Must have good teamwork and interpersonal skills. Graphics Pipeline Experience Is Preferred. Deep knowledge of computer architecture is preferred. Must be a self-starter, and able to independently drive tasks to completion. Preferred Experience Good teamwork and communications skills are required. Minimum 12 Years Of Experience In ASIC Verification Must be proficient in Verilog, System Verilog, UVM Methodologies, and C/C++ programming Academic Credentials B.E/B.Tech or M.E/M.Tech degree in ECE/ Electrical Engineering / Computer Engineering with Digital Systems/VLSI as major with 12+ Years of Exp Location : Hyderabad, India Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer -GLS Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements: Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus TekWissen Group is an equal opportunity employer supporting workforce diversity.

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Design Verification Engineer (7-10 years experience) Company: HCL Tech Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

Exp: 3 to 15 Yrs Location: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamenta lsHands on experience in System Design with FPGA devices with relevant FPGA EDA too lsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPG AsWrite high quality code in Verilog/System Verilog, VHDL and C code for embedd edprocessors. Maintain existing cod e.Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/V IPExperience in using Synthesis, Placement constrain tsSTA constraint definition and Timing closure for high speed desig nsValidation of FPGA based implementation on HW boa rdExperience in writing embedded FW programs in C/C ++Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debugge rsBe conversant with on-chip debug too lsExperienced with scripting tcl/pe rlExposure to Version management systems, GitHub, S VNExcellent verbal and written communication skills in Engli shStrong technical background in silicon validation, failure analysis and deb ugUnderstand hardware architectures, use models and system level design implementations required to utilize the silicon feature s.

Job Title: Lead FPGA Design Engineer Experience Required: 6+ years Location: Hyderabad/Bangalore Job Type: Full-time Industry: Semiconductor / Electronics / Embedded Systems Job Summary: We are looking for a highly skilled and experienced Lead FPGA Design Engineer to join our hardware design team. The ideal candidate will lead the design, implementation, verification, and validation of FPGA-based systems for complex hardware products. This role involves mentoring junior engineers, collaborating with cross-functional teams, and ensuring delivery of high-performance, high-reliability designs. Key Responsibilities: Lead architecture definition and design of complex FPGA solutions using VHDL/Verilog/SystemVerilog. Translate system-level requirements into FPGA design specifications. Hands-on implementation of FPGA designs using Xilinx, Intel (Altera), or Lattice FPGAs. Develop testbenches and perform simulation using tools like ModelSim, Questa, or VCS. Integrate and validate FPGA designs on hardware, working closely with board design and software teams. Use industry-standard tools such as Vivado, Quartus, Synplify, etc. Lead FPGA timing closure, floor planning, and resource optimization. Perform version control, documentation, and design reviews. Guide and mentor a team of junior engineers; ensure design best practices and quality processes are followed. Required Skills and Experience: Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering. 6+ years of industry experience in FPGA design and verification. Expertise in VHDL/Verilog/SystemVerilog coding and simulation. Experience with FPGA toolchains such as Xilinx Vivado, Intel Quartus, Synplify. Strong knowledge of high-speed interfaces (e.g., PCIe, DDR, Ethernet, AXI). Familiar with embedded processor systems (MicroBlaze, Nios II, ARM SoCs). Proficiency in scripting (Tcl, Python, Shell) for automation. Experience with static timing analysis, constraints definition (SDC), and debugging. Good understanding of hardware/software integration. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications: Prior experience in leading FPGA teams or projects. Exposure to safety-critical or mission-critical design environments (e.g., automotive, aerospace, medical). Experience with hardware emulation or ASIC prototyping on FPGAs. Familiarity with version control systems (Git, SVN) and documentation tools. Why Join Us? Work on cutting-edge FPGA designs in a collaborative environment. Competitive compensation with leadership opportunities. Growth-focused, innovation-driven engineering culture. Interested can share CV to sharmila.b@acldigital.com

Exp level:4+ years Location: Hyderabad/Banglaore Job Title:FPGA Engineer Required skill for the Job:• Basic STA knowledge along with tools like Vivado. • Experience on FPGA platforms like AMD(XILINX)/Altera. • Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs • Experience in scripting language like perl, python and tcl • Working experience on Linux. • Ensure to complete design and timing verification tasks within allotted timelines. • Ability to work individually and in a team Basic Job Deliverable:• Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification • Perform task of debugging design timing related issues on different FPGA families • Perform the work of manifold segmentation of the FPGA designs. • Run internal scripts for performance testing and update scripts when necessary Qualification:BTech/MTech Interested can share CV to sharmila.b@acldigital.com

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Location: Bengaluru, Karnataka Experience: Minimum 3 Years of EdTech/IT/Corporate/Institutions Qualification: BE, BTECH, ME, MTECH, MCA (Any Degree) Shift Timing: 9:00 am to 6:00 pm (Mon to Fri) 9:00 am to 1:00 pm ( Sat) Skills & Requirements: Excellent communication skills written and verbal and negotiation skills. Fluent English speaking is mandatory. Strong Training experience highly preferred in VLSI, Verilog, HDL, VHDL/ Verification / Digital Electronics / Physical Electronics / Analog Electronics. Hands on programming with Verilog, Linux operating systems, Digital system design, SV, UVM, PGA. Knowledge of functioning of academic institutions and placement process . The candidate should have good interpersonal skills and networking in the market. Multi-tier architecture knowledge. Excellent self-management skills (task lists, status reports, prioritization). Commitment to quality and timely deliverable. Desire to understand the business. Roles & Responsibilities: Conduct technical training for graduates, professionals, and corporate employees. Develop customized training content, assessments, and course materials. Organize and deliver college and corporate workshops. Guide hands-on project work and mentor large student groups. Manage complete training lifecycle from analysis to evaluation. Ensure high-quality and effective training delivery. Lead and mentor trainers and developer teams. Coordinate with stakeholders to align training with business needs. Ensuring quality delivery to students. Provide timely feedback and performance evaluation to improve learner outcomes. Provide programming direction to a team of trainers. Job Type: Full-time Pay: ₹35,000.00 - ₹65,000.00 per month Schedule: Day shift Education: Bachelor's (Preferred) Experience: VLSI Trainer: 3 years (Preferred) Verilog: 3 years (Preferred) Edtech: 3 years (Preferred) Language: English (Preferred) Work Location: In person

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"