Field-Programmable Gate Arrays Engineer

🚀 We’re Hiring: Senior FPGA Design Engineer | 7+ Years Experience |

📍Location: Gurugram

5 Days Work from office.

Are you passionate about designing high-performance FPGA systems that power next-generation computing and connectivity?

We’re looking for an experienced FPGA Design & Development Engineer to join our cutting-edge R&D team!

💼 Experience: 7+ Years

🎓 Qualification: B.E / B.Tech / M.Tech in ECE, EE, or related field

🔧 Key Responsibilities:

✅ Design, architect, and develop FPGA RTL (VHDL/Verilog) logic for high-speed serial protocols.

✅ Handle CDC, multi-clock domains, SerDes, and timing closure challenges.

✅ Perform FPGA synthesis, place & route, and timing optimization using Xilinx Vivado.

✅ Validate FPGA and board-level issues, ensuring reliable high-speed interface performance.

✅ Collaborate with global R&D teams and leverage AI-assisted tools (e.g., GitHub Copilot, LLM-based aids) to enhance development productivity.

🧠 Requirements:

🔹 5 to 7 years of hands-on FPGA design & development experience.

🔹 Strong expertise in PCIe, NVMe, CXL, or other serial protocols (Ethernet, USB 3.x, SATA, HDMI, DisplayPort, etc.).

🔹 Experience in timing closure, CDC handling, and interface validation.

🔹 Proficiency with Xilinx Vivado for synthesis and implementation.

🔹 Familiar with simulation tools like ModelSim, Questa, or Vivado Simulator.

🔹 Tier-1 engineering background (IIT/NIT or equivalent) preferred.

🌟 Why Join Us?

Join a global innovation team driving the future of high-speed computing. Collaborate with world-class engineers and work on next-generation FPGA solutions that make a real impact.\

📩 Interested? Apply Now or DM us on disha.bisht@clingmultisolution.org