144 Vivado Jobs

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understanding the project requirements and define architecture/Micro architecture with proper documentation.You will be guiding the team for system development Job Responsibilities : ➢ You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) ➢ Understand the customer requirements and product definition ➢ Define architecture and detailed design spec based on requirements and various trade-offs ➢ Micro-architecture and coding of assigned module in VHDL/Verilog ➢ Write test bench for verifying design for complete scenario coverage ➢ Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement ➢ FPGA debugging and HW/SW integration Requirements: ● 6+ years of experience, including successful completion of FPGA based projects ● Coding experience in VHDL and/or Verilog is must ● Experience targeting Xilinx and/or Altera FPGAs required ● Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required ● Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor ● Implementation of designs with multiple clock domains is required ● Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed ● Experience in RTL implementation of DSP algorithms will be appreciated ● Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated Job Type: Full-time Pay: ₹450,000.00 - ₹580,000.00 per month Schedule: Day shift Ability to commute/relocate: Gurugram, Haryana: Reliably commute or willing to relocate with an employer-provided relocation package (Required) Experience: FPGA: 6 years (Required) Language: English (Required) Location: Gurugram, Haryana (Required)

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understanding the project requirements and define architecture/Micro architecture with proper documentation.You will be guiding the team for system development Job Responsibilities : ➢ You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration. Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G, digital signal processing and control logic (bus interfaces and state machines) ➢ Understand the customer requirements and product definition ➢ Define architecture and detailed design spec based on requirements and various trade-offs ➢ Micro-architecture and coding of assigned module in VHDL/Verilog ➢ Write test bench for verifying design for complete scenario coverage ➢ Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement ➢ FPGA debugging and HW/SW integration Requirements: ● 6+ years of experience, including successful completion of FPGA based projects ● Coding experience in VHDL and/or Verilog is must ● Experience targeting Xilinx and/or Altera FPGAs required ● Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required ● Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor ● Implementation of designs with multiple clock domains is required ● Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed ● Experience in RTL implementation of DSP algorithms will be appreciated ● Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated Job Type: Full-time Pay: ₹450,000.00 - ₹580,000.00 per month Schedule: Day shift Ability to commute/relocate: Gurugram, Haryana: Reliably commute or willing to relocate with an employer-provided relocation package (Required) Experience: FPGA: 6 years (Required) Language: English (Required) Location: Gurugram, Haryana (Required)

As an FPGA Designer in the Research and Development department, you will play a crucial role in defining and developing intricate FPGA designs for AWG & Digitizer products. Working in a dynamic and collaborative environment, you will closely collaborate with the R&D Project Manager, Product Architects, Solution Teams, Software Qualification, and Software Engineers to enhance existing products and introduce new offerings. Your ability to work effectively within a team, including other design teams based in the US & Europe, is essential for success in this role. Key Requirements: - A Bachelor's or Master's degree in Electrical / Electronic Engineering. - 8-10 years of hands-on experience in FPGA development with proficiency in Altera and Xilinx technologies. - Proficiency in RTL languages such as VHDL and Verilog. - Familiarity with Xilinx FPGA Tools Design Flow, including Vivado and Chipscope. - Experience in achieving timing closure for complex designs. - Proficiency in Functional Simulation tools like Synopsys, Mentor, Cadence, or Vivado simulator. - Ability to develop self-checking Simulation environments involving test benches, automation scripts, and test case creation. - Quick adaptability to new technologies and product segments. - Strong written communication skills for creating various technical documents. - Self-motivated, organized, and accountable individual. - Excellent team player with responsive communication skills. Preferred Skills: - Experience in high data throughput real-time processing (~ 1GSPS), PCIe, DDR memories, FSM, etc. - Familiarity with Test & Measurement lab equipment. - Knowledge of C/C++ programming languages. In this role, your expertise and dedication will contribute significantly to the advancement and innovation of FPGA designs for cutting-edge products.,

RTL/FPGA Design Engineer(Experienced). Exp : Min 3- 7 Years of Experience Job Description & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.) Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B. Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. (ref:hirist.tech)

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification using Verilog/System Verilog or VHDL, optimize RTL code to meet timings and on-chip resources, and support all phases of FPGA-based product development activities. System Architecture Design, testing, and troubleshooting of hardware will also be part of your responsibilities. To excel in this position, you must have experience with Verilog/SystemVerilog or VHDL for design and verification, along with a deep understanding of FPGA design flow/methodology, IP integration, and design collateral. You should be capable of developing small IP blocks from scratch and conducting basic functional verification. Familiarity with protocols like SPI, I2C, UART, and AXI, as well as knowledge of Altera Quartus II Tool, Questasim, Modelsim, Xilinx tools like ISE and Vivado, and Microsemi tools like Libero, are essential. Understanding of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash is also required. In terms of personal competencies, you should be self-motivated to learn and contribute, able to work effectively with global teams, and willing to collaborate in a team-oriented environment. Prioritization and execution of tasks to achieve goals in a fast-paced environment, along with strong problem-solving skills, are valuable assets. Your passion for writing clean and neat code that aligns with coding guidelines will be highly appreciated. If you meet these qualifications and are excited about the opportunity to work in the VLSI domain as an RTL/FPGA Design Engineer, we encourage you to apply now.,

You will be joining as a Senior FPGA Engineer professional at our Bangalore location with a minimum of 5 years of experience. In this role, your primary responsibilities will include collaborating with a team of product managers, developers, and testers to define feature requirements, developing feature specifications, and implementing detailed designs using Verilog and FPGA design tools. You will also be involved in problem isolation, fault finding in embedded systems, customer issue replication, and creating/updating release notes. Additionally, you will work closely with onsite and offsite development teams to deliver market-leading products globally and mentor junior engineers in development, code, and debugging. To excel in this role, you must be an expert Verilog/System Verilog developer with strong embedded debugging skills. Proficiency in AMD/Xilinx FPGA with Vivado/Vitis tool-chains for implementations and validation, as well as experience with Xilinx/AMD simulator/ModelSim for unit and system-level simulations, is essential. You should possess excellent analytical skills, adaptability to ambiguity and change, and a thorough understanding of the FPGA development cycle within project-based environments. Experience with modern 32-bit processors/microcontrollers like ARM, debuggers, protocol analyzers, and logic analyzers is required. Desirable skills include expertise in Embedded Linux Kernel and Device Drivers development, familiarity with video and audio codecs such as MPEG4 and JPEG, knowledge of USB protocols, and understanding of network protocol stack concepts like ethernet, IP, and TCP. Strong communication and documentation skills are necessary for this role. If you are interested in this opportunity, please share the following details along with your profile to vijitha.k@blackbox.com: - Total experience: - Relevant experience in FPGA: - Experience in Embedded: - Experience in Linux: - Current CTC: - Expected CTC: - Notice period: - Current Location: - Preferred Location: - Current Company: - Any pending offers: - Educational Qualifications,

Location Karnataka Bengaluru Experience Range 10 - 15 Years Qualification BE (EEE) Job Description FPGA design Engineer Key skills: Design and implement FPGAs used in distributed antenna and OpenRAN wireless systems Perform architecture trade-off analysis based on design requirements Competency in RTL design (VHDL preferred) Knowledge in digital signal processing (e.g. FFT, IFFT, Filter designs) Familiar with multi gigabit packet communication protocols (Ethernet, JESD204, etc.) and corresponding hardware cores in FPGA Experience with AMD (Xilinx) and/or Altera FPGA platforms Experience with design implementation through timing closure Proficiency in simulation tools (e.g., ModelSim, Vivado Simulator) Good-to-Have: Experience with version control tools (e.g., Git, SVN) Familiarity with scripting languages (TCL, Python, etc.). Experience with Matlab/Simulink. PCB bring-up with FPGA builds

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are eager to leave a mark on the technology industry. With over 30 years of expertise in computational software, Cadence stands as a pivotal figure in electronic design. Our Intelligent System Design approach helps us provide software, hardware, and IP solutions that bring design ideas to life. Our clientele comprises the most groundbreaking companies globally, creating exceptional electronic products across various sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare. The Cadence work environment offers a multitude of benefits: - A chance to engage with cutting-edge technology and a culture that fosters creativity, innovation, and impact-making. - Employee-centric policies that prioritize physical and mental well-being, career growth, learning opportunities, and acknowledging achievements based on individual needs. - The "One Cadence One Team" ethos that encourages collaboration within and among teams to ensure customer satisfaction. - A range of learning and development avenues tailored to cater to employees" specific interests and requirements. - Collaborating with a diverse team of enthusiastic, committed, and skilled individuals who consistently go the extra mile for customers, communities, and each other. Job Summary: We seek a professional with over 14 years of experience possessing the following skill set: - Proficiency in RTL design basics utilizing HDLs like VHDL/Verilog/System Verilog. - Comprehensive understanding of AMD (Xilinx) Ultrascale, Versal FPGAs architecture, and experience with Vivado for FPGA place and route. - Competence in defining constraints for FPGAs and conducting Static Timing Analysis. - Familiarity with FPGA prototyping or emulation is advantageous. - Eagerness to learn and explore new technologies, showcasing strong analytical and problem-solving abilities. - Effective written and verbal communication skills, a quick learner, and a team-oriented individual. At Cadence, we are committed to impactful work. Join us in unraveling challenges that others find insurmountable.,

Senior RTL Design Engineers Experience : 3-5 years Location : Hyderabad Strong RTL(verilog/system verilog) skills with experience in IP development. • Ability to verify designs by writing simple testbenches. • Strong foundation in logic synthesis and timing closure concepts. • Good knowledge of SoC architecture, AXI bus protocols, hardware debug. • Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus. Interested,please drop your updated resume to janagaradha.n@acldigital.com

Experience: 4 years Location: Hyderabad FPGA Design: Develop FPGA designs using hardware description languages (HDLs) such as VHDL or Verilog. Implement and optimize complex digital logic circuits for high-performance applications. Synthesis & Optimization: Perform synthesis, place and route, and optimization of FPGA designs to ensure optimal area, performance, and power consumption. Testbench Development & Verification: Develop and execute testbenches for simulation and verification of FPGA designs using tools such as ModelSim, Vivado, or Questa. Ensure designs meet functional, timing, and performance requirements.

Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About The Role We are seeking a skilled FPGA Engineer with 37 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. Kindly share your resume at: hr@advantal.net For more information, connect with us at: 91 91312 95441

Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) Embedded Engineer Advantal Technologies is seeking for the following positions: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in C programming on Bare Metal Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands-on experience on Xilinx Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-178C Experience on device driver development Experience on protocols: I2C, SGMII, UART, SPI Desirable to have experience on security aspects of authentication, certificates, encryption/decryption FPGA Engineer: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands-on experience on Xilinx Vivado and Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-254 Desirable to have experience on Microblaze Desirable to have experience on security aspects of authentication, certificates, encryption/decryption Technical Lead Minimum 8 years of experience. Minimum of 2 years experience in leading teams Excellent understanding of embedded system development and real-time application development. Hands-on experience in bare-metal code development using C, over an embedded platform Hands-on experience of FPGA design flow and experience digital design development using Verilog HDL. Experience in DO-178C compliance and certification Understanding of software development using API, and networking protocols Should be able to address the non-functional aspects like performance, scalability, reliability, availability etc. Should have a good understanding of the security aspects of the applications like authentication, authorization, public key infrastructure, SSL, certificates, etc. Good hands-on with design, coding, and resolving the technical issues Good experience in review process architecture, design, code. Fair understanding and working experience in Qt, C / Java/python programming languages. Technical hands-on with tools and related framework. Strong interpersonal and excellent communication skills. Testers Minimum 3 years of experience in testing of embedded systems. Experience in test case design and related execution. Experience in testing Zynq ultrascale MPSoC using Xilinx Vivado. Experience in writing test bench using Verilog/System Verilog. Experience in QuestaSim or equivalent simulation tool, simulation environment creation, good experience in code coverage, branch coverage. If interested, please contact hr@advantal.net

You are a senior FPGA expert with over a decade of experience in architecting, implementing, and optimizing complex digital systems. Your role will involve owning the design and delivery of mission-critical FPGA-based solutions. You will be responsible for the architecture, design, and implementation of complex FPGAs (Xilinx/Intel), as well as defining and driving system-level hardware architecture in collaboration with cross-functional teams. Additionally, you will lead timing closure, constraint management, and interface integration (PCIe, DDR, high-speed serial), while optimizing performance, power, and resource utilization. Your role will also include providing technical leadership, conducting peer reviews, and mentoring junior engineers. To be successful in this role, you should have 10+ years of hands-on FPGA design experience, deep expertise in Verilog/VHDL/SystemVerilog, and a strong track record of successful tape-outs/productization. Proficiency with tools such as Vivado, Quartus, Synplify, ModelSim, or similar is required. Familiarity with embedded systems, SoCs, or HW/SW integration is considered a plus. The ideal candidate is a self-starter who excels at solving challenging problems, shaping architecture, and delivering production-quality hardware. In this role, you will have the opportunity to work on innovative, performance-critical systems, while enjoying autonomy, ownership, and a voice in architecture decisions. If you are interested or know someone who fits this description, please apply by sending your details to himabindu.jeevarathnam@acldigital.com.,

Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) Embedded Engineer Advantal Technologies is seeking for the following positions: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in C programming on Bare Metal Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands on experience on Xilinx Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-178C Experience on device driver development Experience on protocols: I2C, SGMII, UART, SPI Desirable to have experience on security aspects of authentication, certificates, encryption/decryption FPGA Engineer: Experience band 3-7 years (We can have one lead of experience around 7 and rest 3 years) Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferable ZCU 106/104) Hands on experience on Xilinx Vivado and Vitis Desirable to have experience on MISRA C coding guidelines Desirable to have experience on DO-254 Desirable to have experience on Microblaze Desirable to have experience on security aspects of authentication, certificates, encryption/decryption Technical Lead: Minimum 8 years of experience. Minimum of 2 years experience in leading teams Excellent understanding of embedded system development and real-time application development. Hands-on experience in bare-metal code development using C, over an embedded platform Hands-on experience of FPGA design flow and experience digital design development using Verilog HDL. Experience in DO-178C compliance and certification Understanding of software development using API, and networking protocols Should be able to address the non-functional aspects like performance, scalability, reliability, availability etc. Should have a good understanding of the security aspects of the applications like authentication, authorization, public key infrastructure, SSL, certificates, etc. Good hands-on with design, coding, and resolving the technical issues Good experience in review process architecture, design, code. Fair understanding and working experience in Qt, C / Java/python programming language Technical hands on with tools and related framework Strong interpersonal and excellent communication skills Testers: Minimum 3 years of experience in testing of embedded system Experience in test case design and related execution. Experience in testing Zynq ultrascale MPSoC using Xilinx Vivado Experience in writing testbench using Verilog/System Verilog Experience in QuestaSim or equivalent simulation tool, Simulation environment creation, Good experience in code coverage, branch coverage If interested, please contact hr@advantal.net

Company : Mirafra Software Technologies Pvt Ltd Locations : Hyderabad Experience: 6 to 15 yrs Send your resume to: swarnamanjari@mirafra.com or APPLY Or tag/share with someone actively looking! Lets connect the right talent to the right opportunity! 1) Job Description (5 to 10 yrs) Strong in digital design. • Strong in Xilinx Vivado IP & IPI tools till bit-generation. • Knowledge of VHDL/Verilog/System Verilog. • Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. • Proficiency in Linux environment. • Good communication skills. Basic Job Deliverable : RTL coding, IP design, Modify/update existing IP as per requirements. 2) Job Description (7 to 12yrs) 7 to 12 years of experience in digital design. • RTL coding experience using Verilog and/or System Verilog. • Working experience of AMD/Xilinx FPGA and Vivado. • Experience in Video domain (DisplayPort/MIPI) is preferred. • Candidate shall be working at AMD Sattva site, Hyderabad. 3) Job Description (2 to 4yrs) Design Creation and Analysis profile with RTL, STA, Scripting and FPGA flow (Vivado/ Quartus/ Lattice). Education & Other Requirements B.Tech / M.Tech / BE in Electronics, Electrical, ECE or equivalent

Role : RTL Software Testing Engineer Role does not involve Silicon RTL development and neither any HW flow or testing. Work Location: Hyderabad Qualification: B.E / B. Tech or M. Tech in ECE / CS / EEE Experience Level : Minimum 2+ years Job Description Excellent Knowledge in Tcl, Python scripting. to test cases.(This would be the primary responsibility) Vivado testing of synthesis tool and other stages. RTL Coding in Verilog, System Verilog, or VHDL Strong understanding of FPGA flow, Logic design, Digital design etc. Knowledge in Xilinx FPGA architecture Communication Skills: Ability to communicate technical information in an organized and understandable fashion. Customer oriented approach with a demonstrated concern and desire to work with and assist customers. Good organizational skills with the ability to multitask, prioritize, and track many activities. Outstanding oral and written communication skills.

Company Description ACL-Apollo Computing Laboratories (P) Ltd. is a leading manufacturer of high-quality electronic systems specializing in embedded computing. Established in 1992 in Hyderabad, we focus on engineering and quality assurance to achieve excellence. Our in-house developed products are qualified for military standards and widely used in defense and aerospace. Join us in revolutionizing the embedded computing landscape with innovative solutions that exceed expectations. Role Description We are looking for an FPGA Design Engineer to design and develop FPGA-based solutions using VHDL. You will work with Xilinx FPGA platforms, utilizing tools such as Vivado, Libero SoC, and Questasim to create and verify complex digital designs. Your role will involve implementing communication protocols (1553B, RS422, RS232, serial, parallel and other protocols), optimizing performance, and collaborating with cross-functional teams to ensure seamless integration and functionality. Qualifications Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred). Proven experience with Xilinx FPGAs and HDL design Proficiency with Vivado, Libero SoC, and Questasim. Strong understanding of communication protocols and timing analysis. Experience in 1553B, RS422, RS232, ARINC 429 or AFDX protocols are a major plus Strong problem-solving and analytical skills Excellent communication and teamwork abilities

As an RTL/FPGA Design Engineer in the VLSI domain, you will play a crucial role in developing FPGA-based products. With a focus on RTL programming using Verilog/System Verilog or VHDL, you will be responsible for optimizing RTL code to meet timing requirements and on-chip resource constraints. Your expertise in FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, and Libero will be essential in ensuring the successful completion of projects. Your responsibilities will include functional verification using Verilog/System Verilog or VHDL, system architecture design, and testing/troubleshooting of hardware components. Additionally, you will be required to support all phases of FPGA-based product development activities, demonstrating a strong understanding of FPGA design flow/methodology and IP integration. To excel in this role, you should hold a BE/B.Tech or ME/M.Tech degree in Electronics/Electronics & Communication or Electronics/VLSI Design from a recognized university. Proficiency in Verilog/SystemVerilog or VHDL for design and verification is essential, along with knowledge of protocols like SPI, I2C, UART, and AXI. Familiarity with tools such as Quartus II, Questasim, Modelsim, ISE, Vivado, and libero will be advantageous. As a self-motivated individual, you should be eager to learn and contribute effectively within a team-oriented environment. Your ability to prioritize tasks, solve problems creatively, and write clean code following coding guidelines will be highly valued. If you are passionate about working in a dynamic and innovative setting, we encourage you to apply for this exciting opportunity in Ahmedabad or Bangalore. Join us and be a part of our vibrant team dedicated to pushing the boundaries of VLSI design and FPGA technology. Apply now to explore this role further and take the next step in your career growth.,

As part of our team working on building India's first commercial Scanning Electron Microscope (SEM) from scratch, your primary responsibility will be to design and develop the real-time beam controller on a Zynq Ultrascale+ (ARM+FPGA). You will be working on achieving a pixel clock of 20 MHz with 5 ns jitter, ensuring a blanking rise/fall time of less than 25 ns into 50. Additionally, you will implement closed-loop stage control utilizing high-resolution position feedback and update the PID at a frequency of 10 kHz. Your role will also involve streaming 16-bit detector data at a rate of 250 MB/s over PCIe to host memory. Furthermore, you will be tasked with delivering imaging algorithms such as auto-focus, auto-stigmation, and drift correction that run at 5 frames per second. To facilitate scripting and automated metrology, you will need to develop a clean and well-documented Python API. To excel in this role, you should possess at least 6 years of experience in C++17/C, Python, real-time Linux or RTOS. You should be comfortable working with FPGA toolchains like Vivado and Verilog. A strong background in DSP and control theory is essential, and you should be adept at using tools like scope probes and logic analyzers. Any prior experience with SEM, TEM, or other charged-particle systems would be considered a bonus. We are interested in learning about the most challenging technical problem you have successfully tackled and why you are excited about contributing to Bharat Atomic's mission. If you are passionate about turning first-principles physics into a manufacturable instrument and possess the required skills and experience, we encourage you to share your CV and Portfolio with us.,

Role & responsibilities Design and Development : Develop and implement FPGA architectures and digital circuits using VHDL or Verilog. Write RTL code and testbenches to meet functional and performance requirements. Perform synthesis, place-and-route, and timing analysis to ensure design closure. Simulation and Verification : Simulate designs using tools like ModelSim, Questa, or Vivado Simulator to validate functionality. Create and execute test plans on hardware test benches to verify FPGA designs. System Integration : Collaborate with hardware, software, and system engineers to integrate FPGA designs into larger systems. Debug and troubleshoot FPGA implementations using tools like logic analyzers, oscilloscopes, and JTAG. Optimization : Optimize FPGA designs for speed, resource utilization, and power efficiency. Ensure signal integrity and timing constraints are met for high-speed interfaces. Documentation : Document design processes, specifications, and test results for compliance and future reference. Participate in design reviews and provide technical input. Continuous Improvement : Stay updated with the latest FPGA technologies, tools, and methodologies. Propose and implement improvements to design workflows and processes. Qualifications and Skills : Education : Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience : 4-6 years of professional experience in FPGA design, development, and verification. Proven track record of delivering FPGA-based projects from concept to production. Technical Skills : Proficiency in HDL languages (VHDL and/or Verilog/SystemVerilog). Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, or Microchip Libero. Strong understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Familiarity with high-speed communication protocols (e.g., PCIe, Ethernet, USB, JESD204B). Experience with simulation tools (e.g., ModelSim, Questa, or VCS). Knowledge of scripting languages (e.g., Python, TCL, or Perl) for automation. Familiarity with embedded systems and hardware-software co-design is a plus. Soft Skills : Strong problem-solving and analytical skills. Ability to work independently and collaboratively in a team environment. Excellent communication skills for technical discussions and documentation Preferred candidate profile Experience in a regulated industry (e.g., aerospace, defence, or medical devices). Knowledge of digital signal processing (DSP) or high-speed digital design. Familiarity with SoC architectures (e.g., Xilinx Zynq, Intel Cyclone) and IP integration. Experience with version control tools (e.g., Git, SVN).

Job Description: We are hiring an RTL Design Engineer with hands-on experience in FPGA-based RTL development. This role is focused on FPGA logic design and does not involve Silicon RTL or hardware testing . Key Responsibilities: RTL coding using Verilog, SystemVerilog, or VHDL Work on FPGA architecture and flow , including logic and digital design Scripting with Tcl and Python Perform synthesis and design stages using Vivado Collaborate with design teams to deliver high-quality IP blocks for FPGA

We are building India's first commercial Scanning Electron Microscope (SEM) from the ground up. This is not an integration project. We will design our own electron optics, high-voltage systems, precision mechanics, and real-time control software. If the idea of turning first-principles physics into a manufacturable instrument excites you, read on. Your Mission Build the real-time beam controller on a Zynq Ultrascale+ (ARM+FPGA): Pixel clock ≤20 MHz with ±5 ns jitter; Blanking rise/fall <25 ns into 50 Ω Implement closed-loop stage control using high-resolution position feedback; update PID at 10 kHz. Stream 16-bit detector data at 250 MB/s over PCIe to host memory. Ship imaging algorithms: auto-focus, auto-stigmation, drift correction running at ≥5 fps. Provide a clean, documented Python API for scripting and automated metrology. Who You Are 6+ yrs C++17/C, Python, real-time Linux or RTOS; comfortable inside FPGA toolchains (Vivado, Verilog). Solid DSP & control theory background; not afraid of scope probes or logic analyzers. Bonus: prior work on SEM, TEM, or other charged-particle systems. Share the hardest technical problem you have solved and why Bharat Atomic's mission fires you up along with your CV and Portfolio.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities -Debug and solve U-Boot issues. -Enhance U-Boot to meet the new customer requirements. contribute to upstream U-Boot with the client changes. Skills Must have 4 to 7 years of C programming experience. 4 to 7 years U-Boot driver development experience. Or 4 to 7 years any firmware driver development experience. Should have Linux Drivers Development knowledge Good System Level knowledge Good debugging skills Nice to have Good Communication skills. Usage of Tool Vivado is an added advantage

You are an experienced FPGA design engineer with over 3 years of experience, based in Vadodara, India. Your primary responsibility will be implementing control logic state machines and DSP algorithms in FPGA fabric for high throughput systems. You must possess excellent troubleshooting and debugging skills for both simulation and in-circuit scenarios. Your expertise should include continual integration of unit modules into FPGA top-level design, using SignalTap to debug logic and/or timing issues, constructing bypasses, data taps, and data pattern generators for isolation, managing timing closure and constraints files, and creating basic glue logic between DSP blocks. You should also be capable of power estimation pre and post-implementation, working closely with board designers for optimal pin-out mappings, and collaborating with software team members to develop, execute, and debug unit and system-level verification tests. Your technical skills should encompass working with HDL simulation tools like ModelSim, Verilog HDL/VHDL languages, Xilinx/Altera FPGAs using Quartus II/Vivado/ISE, and SignalTap/Chipscope for debugging. Additionally, you should be comfortable taking ownership of projects and related tasks. Experience with SoC and QSYS, protocols such as AMBA, AXI, Avalon, USB, PCIe, memory interfaces like DDR2/DDR3/DDR4, and control buses like I2C and SPI/QSPI would be beneficial. About A&W Engineering Works, the organization's mission is to develop and deploy innovative solutions to real-world problems. The team at A&W Engineering Works specializes in developing complete systems from front-end sensors to back-end applications, including analog, digital signal processing, algorithmic data, and control paths. The team's expertise spans hardware, software, mechanical, and system development, enabling them to tackle complex challenges with innovative development techniques. To apply for this role, please send your resume and cover letter to [email protected] with the job title in the subject line.,

The ideal candidate for the FPGA Engineer position in Hyderabad/Bangalore should have a minimum of 4 years of experience in the field. You should possess basic STA knowledge and be proficient in using tools like Vivado. Your expertise should extend to FPGA platforms such as AMD(XILINX) and Altera. Additionally, you should be skilled in digital hardware designing using Verilog on large AMD(Xilinx)/Altera FPGAs. Proficiency in scripting languages like perl, python, and tcl is essential for this role. Experience in working with Linux operating systems is also required. You will be responsible for completing design and timing verification tasks within specified timelines. The ability to work both independently and as part of a team is crucial for success in this role. Your primary job deliverables will include designing, implementing, testing, integrating, and delivering system-level digital designs for FPGA blocks timing verification. You will also be tasked with debugging design timing related issues on various FPGA families and segmenting FPGA designs effectively. In this role, you will run internal scripts for performance testing and update them as needed. A BTech/MTech qualification is necessary to be considered for this position. If you meet these requirements and are interested in the opportunity, please share your CV with sharmila.b@acldigital.com.,