Field-Programmable Gate Arrays Engineer

As a Senior FPGA Design Engineer with 7+ years of experience, you will be responsible for designing high-performance FPGA systems for next-generation computing and connectivity. Your key responsibilities will include: - Designing, architecting, and developing FPGA RTL (VHDL/Verilog) logic for high-speed serial protocols. - Handling CDC, multi-clock domains, SerDes, and timing closure challenges. - Performing FPGA synthesis, place & route, and timing optimization using Xilinx Vivado. - Validating FPGA and board-level issues to ensure reliable high-speed interface performance. - Collaborating with global R&D teams and leveraging AI-assisted tools to enhance development productivity. To qualify for this role, you should have: - 5 to 7 years of hands-on FPGA design & development experience. - Strong expertise in PCIe, NVMe, CXL, or other serial protocols. - Experience in timing closure, CDC handling, and interface validation. - Proficiency with Xilinx Vivado for synthesis and implementation. - Familiarity with simulation tools like ModelSim, Questa, or Vivado Simulator. - A Tier-1 engineering background (IIT/NIT or equivalent) is preferred. Joining this company will allow you to be part of a global innovation team driving the future of high-speed computing. You will collaborate with world-class engineers and work on next-generation FPGA solutions that make a real impact. If you are interested, apply now or contact us at disha.bisht@clingmultisolution.org.,