Taras system and solution

As a skilled and detail-oriented Design Verification Engineer, you will be joining our hardware development team to verify the functionality, performance, and reliability of digital designs (ASIC, FPGA, or SoC) before tape-out or deployment. Your responsibilities include developing and executing verification plans, creating testbenches, performing coverage analysis, debugging design issues, collaborating with cross-functional teams, contributing to testing flows, documenting processes, and assisting with post-silicon validation if needed. Key Responsibilities: - Develop and execute verification plans based on design specifications and architecture documents. - Create testbenches and write test cases using industry-standard verification languages such as SystemVerilog (UVM), Verilog, or VHDL. - Perform functional and code coverage analysis to ensure thorough verification. - Debug RTL design issues by simulating and analyzing failures. - Work closely with design, architecture, and validation teams to understand design intent and root cause issues. - Contribute to the development and automation of simulation and regression testing flows. - Document verification processes, results, and provide input to improve verification methodologies. - Assist with post-silicon validation if required. Qualifications: - Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. - 2+ years of experience in digital design verification (entry-level candidates with strong project/internship experience also considered). - Proficiency in SystemVerilog, UVM/OVM, Verilog, or VHDL. - Experience with simulation tools (e.g., Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa). - Solid understanding of digital design concepts (FSMs, pipelining, timing, etc.). - Familiarity with scripting languages such as Python, Perl, or Tcl for automation. In addition, the following are some preferred skills for the role: - Experience with ASIC or SoC verification flows. - Knowledge of formal verification techniques and tools. - Exposure to low-power or performance verification strategies. - Familiarity with bus protocols such as AXI, AHB, PCIe, USB, etc. - Experience with FPGA-based prototyping or emulation platforms.,