Job Location : HYderabad Experince Level 4+ years The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable). Show more Show less
Experience: 5+Years Job Location : Hyderabad The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Educational Qualification: · Bachelor major in electronics, embedded programming, ECE, EEE. Key Requirements: · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code · coverages. · Experience in FPGA design and FPGA EDA tools will be a plus. · Experience in scripting, such as TCL, Perl, Bash and python to automate the verification · methodologies and flows. · Able to build and set up scalable simulation / verification environments. · Ability to focus on finding the design issues and corner cases. · Knowledge of version control systems (GIT is preferable). · Knowledge of invoking the MATLAB DPI checker (or any foreign language) in the UVM
Job description Hiring : Staff Verification engineers ExperienceLevel :7+Years Job Location : Hyderabad Role Description The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage. Qualifications · Experience in ASIC/FPGA verification using System Verilog. · Develop and sign off on test plans and test cases. · Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++. · Experience in AMBA AHB/AXI/APB based IPs design/verification. · Experience in usage of assertions, constrained random generation, functional and code coverages · Formal Verification and Functional Verification skills · RTL Design and Computer Architecture skills · Debugging skills · Bachelor's or Master's degree in Electrical Engineering or related field
Company Description NG-RAN IIT Hyderabad is renowned for leading India's contributions to 5G global wireless standards, submitting over 400 technical papers to 3GPP work groups from 2017 to 2021. The team has developed several 5G standard-essential patents, including the innovative "pi/2 BPSK with spectrum shaping" technology. With funding from DoT and MeitY, IITH successfully developed prototypes for 5G base stations, user equipment, and NB-IoT System-on-Chip. WiSig Networks Pvt Ltd, a start-up at IITH's technology incubator, is commercializing these IPs and products. As India looks toward 6G technology, NG-RAN IIT Hyderabad plays a crucial role in defining future wireless standards. Role Description This is a full-time on-site role for an RTL Design and Verification Engineer located in Hyderabad. The engineer will be responsible for creating and verifying RTL designs, performing formal and functional verification, and debugging designs to ensure they meet specified requirements. Daily tasks include collaborating with cross-functional teams, developing design specifications, and validating design performance. Exp Level :4+Years Responsibilities: Architecture exploration and Micro-architecture development RTL design and integration for 5G NR UE systems using Verilog/System Verilog Collaboration with multi-discipline teams to integrate, test and debug the designs on FPGAs Required Qualifications: Master's/Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, or equivalent practical experience Skills/Experience Required Strong Domain Knowledge on RTL Design, implementation, and integration for FPGA based designs. Experience with RTL coding using Verilog/System Verilog. Proficiency in complete FPGA design flow . Experience with protocols like AXI4-stream and AXI4 . Exposure in scripting (Python/TCL). Strong debugging capabilities at RTL simulation and FPGA Emulation. Proficiency in version control tools like GIT . Preferred Experience Experience with Intel or Xilinx FPGAs, especially MPSoC FPGAs Experience in Fixed-point arithmetic implementation in Verilog Experience with high-speed serial communication IPs on FPGAs Experience in implementing DSP algorithms RTL Development for wireless communication systems (Most preferably 5G NR)