Synthesis & STA Engineers

As a Synthesis & STA Engineer, your role will involve performing RTL Synthesis to optimize the Performance/Power/Area of designs, implementing DFT insertions such as MBIST and SCAN, setting up Timing Constraints for functional and Test Modes, and conducting Validation. You will be responsible for creating Power Intent for designs, verifying power intent on RTL, running static Low-Power checks on gate level netlists, ensuring Logic Equivalency Checks between RTL to Gates and Gates to Gates, configuring signoff Static Timing Analysis and ECO flows, and achieving timing closure in collaboration with the Design/DFT/PD teams. Additionally, you will be involved in Power Analysis, estimating power at RTL level, executing Sign off Power Analysis on the P&R data, supporting the DV team in gate level simulations with SDF and UPF aware simulations, and facilitating functional eco rollout with automated ECO flows. **Key Responsibilities:** - Perform RTL Synthesis to optimize Performance/Power/Area of designs - Implement DFT insertions including MBIST and SCAN - Set up Timing Constraints for functional and Test Modes - Create Power Intent for designs and verify power intent on RTL - Run static Low-Power checks on gate level netlists - Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates - Configure signoff Static Timing Analysis and ECO flows - Achieve timing closure working with the Design/DFT/PD teams - Conduct Power Analysis and estimate power at RTL level - Execute Sign off Power Analysis on the P&R data - Support DV team in gate level simulations with SDF and UPF aware simulations - Facilitate functional eco rollout with automated ECO flows **Qualification Requirements:** - Minimum 3 years of experience - Experience with Synopsys tools for ASIC Synthesis, Timing Constraints, and DFT implementation (MBIST and Scan) - Proficiency in sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks - Familiarity with Verilog and System Verilog - RTL design experience with Perl/TCL/Makefile scripting - Experience with Power Analysis using Power Artist and PTPX - Exposure to full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows In addition to the above qualifications, the ideal candidate should possess a Bachelor's degree in Electronics and Communications Engineering, Electrical Engineering, or a related field. A Master's degree in VLSI or a related field would be preferred. (Note: No additional details of the company were provided in the Job Description),