Senior/Lead Asic Verification Engineer

You are being sought out as an experienced Senior/Lead ASIC Verification Engineer to join the Bangalore VIP team. With 4 to 15 years of experience across multiple roles, you are expected to have a strong background in Verification, particularly using industry-standard protocols and methodologies. Your proficiency should include hands-on experience with System Verilog and Verilog, along with a solid understanding of Object-Oriented Programming. Your responsibilities will include, but are not limited to: - Contributing to the development of the VIP - Reviewing and providing sign-off on VIP development and updates from a technical perspective, encompassing methodology and protocol functionalities - Collaborating with Architects and methodology experts to address issues and drive output from an architecture/methodology standpoint To excel in this role, you should have played a significant role in developing reusable Verification environments for at least two verification projects using VMM, OVM, or UVM methodologies. Additionally, you should possess protocol experience, particularly in UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocols. If this opportunity aligns with your skill set and career aspirations, please share your updated CV with taufiq@synopsys.com or refer individuals who might be interested. Inclusion and Diversity are core values at Synopsys. They consider all applicants for employment without bias based on race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,