Senior/Lead Asic Verification Engineer

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, you will be involved in utilizing industry-standard protocols and methodologies. Your proficiency in System Verilog and Verilog, along with a solid understanding of Object Oriented Programming, will be essential for this role. As a Senior/Lead ASIC Verification Engineer, you will have the opportunity to lead the development of reusable Verification environments for a minimum of 2 projects using VMM, OVM, or UVM methodologies. Your expertise in protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocol will be valuable. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development updates, and collaborating with Architects and methodology experts to address issues and enhance output from an architecture/methodology perspective. If you are a proactive and reliable professional with a passion for Verification, we encourage you to share your updated CV with us at taufiq@synopsys.com or refer individuals who would be interested in this opportunity. At Synopsys, we value and promote Inclusion and Diversity, and we welcome applicants from diverse backgrounds without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,