Test Engineer

HCLTech

10 years

0 Lacs

Kochi Kerala India

Posted:1 week ago| Platform:

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Skills Required

test dft architecture atpg logic resolve drc analyze support synthesis simulation design verification compliance synopsys scripting tcl perl python coding verilog systemverilog timing constraints power simulations

Work Mode

On-site

Job Type

Full Time

Job Description

Key Responsibilities:

Define and implement DFT architecture for SoCs and IPs.
Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG).
Work with RTL designers to insert DFT logic and resolve DRC violations.
Generate and validate test patterns using tools such as
TetraMAX
,
FastScan
,
DFT Advisor
, etc.
Analyze and improve fault coverage and test time reduction.
Support silicon bring-up and post-silicon validation of test features.
Debug and resolve DFT-related issues during synthesis, simulation, and verification.
Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow.

Required Skills:

3–10 years of hands-on experience in DFT implementation.
Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan.
Experience with DFT tools:
Synopsys DFT Compiler
,
TetraMAX
,
Mentor Tessent
,
FastScan
,
DFTMAX
, etc.
Proficient in scripting (TCL, Perl, Python, Shell) for automation.
Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow.
Good understanding of timing constraints, STA, and low-power design considerations in DFT.
Experience in handling gate-level simulations and testbench development.

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