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Test Engineer

Test Engineer

Best NanoTech

8 years

0 Lacs

bengaluru karnataka india

Posted:1 week ago| Platform:

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Skills Required

test dft architecture stitching atpg analysis algorithms verification checks linting resolve simulations support timing collaboration engineering compensation diversity

Work Mode

On-site

Job Type

Full Time

Job Description

About the Role

Position: Lead DFT Engineer

Experience: 8+ years

Responsibilities

Develop and implement DFT architecture for complex SoCs and IPs.
Perform Scan Insertion, Scan Stitching, and Scan Chain Optimization.
Execute ATPG pattern generation, compression, coverage analysis, and pattern debug.
Implement and validate MBIST/BIST architectures, including memory test algorithms and integration.
Work closely with RTL, PD, and Verification teams to ensure DFT features are seamlessly integrated.
Perform DFT rule checks, linting, and resolve violations.
Conduct gate-level simulations for DFT verification (DFT-GLS).
Support timing closure for DFT modes in collaboration with STA teams.
Generate high-quality test patterns for production test and support bring-up teams during silicon validation.

Qualifications

Education details: Engineering or equivalent

Required Skills

ATPG
Scan Insertion
MBIST
DFT Architecture
STA (DFT mode)
Debug

Pay range and compensation package

Pay range or salary or compensation as per standard

Equal Opportunity Statement

Include a statement on commitment to diversity and inclusivity.

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