2263 Synthesis Jobs - Page 34

Exp: 3 to 15 Yrs Location: Hyderabad / Bangalore The core skill set expected from the team is : Exceptional Digital fundamenta lsHands on experience in System Design with FPGA devices with relevant FPGA EDA too lsExperience in designing and implementing FPGA based solutions in Microchip or Xilinx or Altera FPG AsWrite high quality code in Verilog/System Verilog, VHDL and C code for embedd edprocessors. Maintain existing cod e.Developing testbenches using Verilog/System Verilog and verifying validation designs in simulation environment using BFM/V IPExperience in using Synthesis, Placement constrain tsSTA constraint definition and Timing closure for high speed desig nsValidation of FPGA based implementation on HW boa rdExperience in writing embedded FW programs in C/C ++Strong Lab debug experience and enthusiasm & patience to solve systems level hardware issues using Lab equipment, Embedded debuggers and RTL debugge rsBe conversant with on-chip debug too lsExperienced with scripting tcl/pe rlExposure to Version management systems, GitHub, S VNExcellent verbal and written communication skills in Engli shStrong technical background in silicon validation, failure analysis and deb ugUnderstand hardware architectures, use models and system level design implementations required to utilize the silicon feature s.

Job Responsibilities: 1. Develop a 3-5 year sales strategy for the Indian API market, covering small molecule drugs, intermediates and other sub-sectors. 2. Lead technical cooperation negotiations with the top 20 pharmaceutical companies and CMO/CDMOs. 3. Establish high-level customer relationships and promote the signing of long-term strategic agreements. 4. Guide customers to understand data such as API synthesis routes, impurity profiles, and crystal form studies. 5. Collaborate with R&D/quality departments to solve customer technical issues (such as ICH Q7 compliance, DMF document support). Requirements: 1. Bachelor's degree or above in chemistry, medicinal chemistry, pharmaceutical engineering or related fields. 2. Business communication skills in English. 3. Over 8 years of experience in API/intermediate sales. 4. Successful operation of high-barrier API projects (such as high-activity compounds, peptides, complex synthetic processes). 5. Proficient in the entire API development process: from preclinical process development to commercial production knowledge. 6. Familiarity with Indian GMP regulations. 工作职责: 1. 为印度原料药市场制定3-5年的销售战略，包括小分子药物、中间体和其他细分行业。 2. 主导20强制药公司及CMO/ cdmo的技术合作谈判。 3. 建立高水平的客户关系，促进长期战略协议的签订。 4. 指导客户了解数据，如原料药合成路线，杂质分布和晶体形式的研究。 5. 与研发/质量部门合作解决客户技术问题（如ICH Q7符合性，DMF文件支持）。 要求: 1. 本科以上学历，化学、药物化学、制药工程或相关专业。 2. 商务英语沟通技巧。 3. 8年以上原料药/中间体销售经验。 4. 成功操作高屏障API项目（如高活性化合物、多肽、复杂合成工艺）。 5. 精通原料药开发的整个流程：从临床前工艺开发到商业化生产知识。 6. 熟悉印度GMP法规。

Safran est un groupe international de haute technologie opérant dans les domaines de l'aéronautique (propulsion, équipements et intérieurs), de l'espace et de la défense. Sa mission : contribuer durablement à un monde plus sûr, où le transport aérien devient toujours plus respectueux de l'environnement, plus confortable et plus accessible. Implanté sur tous les continents, le Groupe emploie 100 000 collaborateurs pour un chiffre d'affaires de 27,3 milliards d'euros en 2024, et occupe, seul ou en partenariat, des positions de premier plan mondial ou européen sur ses marchés. Safran est la 2ème entreprise du secteur aéronautique et défense du classement « World's Best Companies 2024 » du magazine TIME. Descriptif mission Mission Manage the operational performance (Logistics & Quality) of suppliers. Deploy supplier development initiatives. Co-ordinate, lead and manage multifunctional teams to ensure collaboration and engagement with all vendor stakeholders. The Supplier Performance Management role is a strategic position and the mindset of forward, analytical and critical thinking is a necessity. A robust and healthy supply base is paramount to our continued and future success. As such, this is exciting role will allow you to utilize your vendor management experience and skill set to propel us forward, meet our objectives/goals and successfully fulfill our customers' requirements. Main Activities Evaluate the level of supplier risk, define and deploy the associated monitoring plans, including supporting ramp-up / down phases and the introduction of new products and dual source implementation. Manage and analyze the logistics and quality performance of suppliers; issue monthly scorecards based on performance utilizing the measurements of KPIs. Determine and lead the escalation and de-escalation process as required based on vendor's performance. Manage and support supplier maturity upgrading plans and promote best practices. Challenge industrial scheme, cycle and lead times, capacity management, routings, and bottleneck management. Support suppliers in the implementation of progress plans in line with SAFRAN's objectives and customer requirements. Arrange and conduct performance audits and assessments, proactively identifying concerns/issues; develop and monitor action plans to mitigate. Participate in the evaluation of suppliers during the vendor selection process. Supply chain principles and tools, including performance audits. Load/Capacity, Rate Readiness Assessment, Line of Balance Analysis, Recovery Plan Management, Business Continuity Plans Understanding of quality standards such as ISO/AS Skills Cross-functional project management, multidisciplinary team work. Negotiation and contracts Change management Good level of written and oral English Master of intercultural relationships. Qualities Communication and listening, sense of the field, pragmatic. Rigor, spirit of analysis and synthesis. Pleasant soft skills. Power of persuasion. Ability to communicate and represent the company externally. Ability to effectively communicate and present to senior management, internal and external. Frequent travel required (max 30%)

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 10+ years of experience in physical design using industry EDA tools. Lead Sub System/SOC physical design for at least 1 product. Experience in Python/Perl/TCL programming languages. Experience in signoff domains (timing, IR-RV. Power, Layout Verification) is an added advantage. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Educational Qualifications B.Tech/M.Tech in Electrical/VLSI/Computer science with relevant experience Preferred Qualifications At least 5+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Safran est un groupe international de haute technologie opérant dans les domaines de l'aéronautique (propulsion, équipements et intérieurs), de l'espace et de la défense. Sa mission : contribuer durablement à un monde plus sûr, où le transport aérien devient toujours plus respectueux de l'environnement, plus confortable et plus accessible. Implanté sur tous les continents, le Groupe emploie 100 000 collaborateurs pour un chiffre d'affaires de 27,3 milliards d'euros en 2024, et occupe, seul ou en partenariat, des positions de premier plan mondial ou européen sur ses marchés. Safran est la 2ème entreprise du secteur aéronautique et défense du classement « World's Best Companies 2024 » du magazine TIME. Descriptif mission Mission Identifies, suggests and implements the development of purchasing strategies and Supplier Performance Management under supervision of the Purchasing and Supply Chain Director Summary of Duties (Sourcing Leader) Contributes to establish and formalize the SAFRAN Group India purchasing strategy and road map for each commodity in collaboration with the Purchasing Department Monitor market evolution and develop purchasing marketing Controls costs and proposes solutions to meet our competitiveness commitments and program objectives Identifies and evaluates new sources and suppliers in order to support the localization targets of Safran India Launches RFQs with identified suppliers and lead negotiations in collaboration with other commodity purchasing leaders within Safran entities Performs supplier selection committee in collaboration with multi-functional team Formalizes and contributes to establish purchasing contracts (General Terms Agreements and Price & Logistics Agreements) with new suppliers Manages existing contracts with current suppliers and ensures compliance with terms and conditions Supports new product introduction by sourcing parts to relevant supplier in each commodity involved Assigns purchasing and scheduling duties based on business requirements Works proactively to optimize purchasing costs Summary of Duties (Supplier Performance Manager) Drives operational excellence and support Supply Chain by improving supplier performance Coordinates the supplier multi-functional team in collaboration with the Supply Chain Manager Monitors and manages the quality and logistics performance of suppliers Identifies root causes of non-performance and establishes action plans Guarantees the consistency of improvement actions initiated by all Supply Chain players in charge of suppliers Measures and communicates (internally and externally) the overall performance (OTD, DOD and PPM) through scorecards and steering meetings Defines and manages the monitoring plan, based on the risk analyses made with the supplier multifunctional team Plans and manages maturity audits and supplier evaluations Leads load/capacity and rate assessments at the suppliers. Defines and monitors action plan accordingly Works proactively to optimize supply chain operations through creative solutions Supply chain principles and tools, including performance audits Load/Capacity, Rate Readiness Assessment, Line of Balance Analysis, Recovery Plan Management, Business Continuity Plans Understanding of quality standards such as ISO/AS Skills Cross-functional project management, multidisciplinary team-work. Negotiation and contracts Change management Good level of written and oral English Master of intercultural relationships. Qualities Communication and listening, sense of the field, pragmatic. Rigor, spirit of analysis and synthesis Power of persuasion Ability to communicate and represent the company externally Ability to effectively communicate and present to senior management, internal and external Frequent domestic travel required (max 30%)

Industry & Sector We are a rapidly scaling player in the global Digital Publishing & EdTech sector, delivering expertly crafted educational content to universities, K-12 platforms, and lifelong learners worldwide. Our multidisciplinary teams turn scholarly expertise into engaging multimedia learning experiences, distributed across web, mobile, and print channels. Operating fully remote, we prize intellectual rigor, creative flair, and data-driven decision making. Role: Content Writer – Literature Specialist Role & Responsibilities Create research-backed articles, study guides, and marketing assets on classic and contemporary English literature that meet C1 linguistic standards and in-house SEO guidelines. Perform deep textual analysis, comparative criticism, and secondary-source synthesis to generate original, plagiarism-free copy suitable for academic and popular audiences. Own end-to-end content lifecycle—ideation, outline, drafting, peer review, revision, and CMS publication—while meeting weekly throughput targets. Collaborate with editors, instructional designers, and growth marketers to align tone, pedagogy, and keyword strategy. Maintain rigorous citation integrity using MLA/APA/Chicago styles and ensure compliance with anti-plagiarism tooling. Coach junior writers and subject-matter freelancers, sharing best practices in narrative flow, voice consistency, and fact-checking. Skills & Qualifications Must-Have Ph.D. in English Literature or related humanities discipline. Native-level or certified C1 English proficiency with demonstrable publication record. 3+ years professional content writing or academic publishing experience. Expertise in close reading, critical theory, and genre-specific stylistics. Hands-on SEO keyword research, on-page optimization, and content analytics tools (Surfer, SEMrush, Google Analytics). Mastery of MS Office or Google Workspace and at least one CMS (WordPress, Contentful, or similar). Preferred Experience developing MOOCs or e-learning modules. Familiarity with AI-assisted writing and version control workflows (Git). Benefits & Culture Highlights 100% remote, flexible hours with asynchronous collaboration. Annual learning stipend for conferences, journals, and upskilling. Peer community of scholars, writers, and technologists who value autonomy and impact. Skills: curriculum design,critical theory,c1 english proficiency,english,seo keyword research,content analytics tools (surfer, semrush, google analytics),ph.d. in english literature,seo copywriting,academic writing,cms (wordpress, contentful or similar),english literature,native-level english proficiency (c1),content analytics tools,google workspace,on-page optimization,content writing,literature,ph.d. in english literature or related humanities discipline,genre-specific stylistics,cms (wordpress, contentful),academic publishing,close reading,ms office

Job Description As a member of the Support organization, your focus is to deliver post-sales support and solutions to the Oracle customer base while serving as an advocate for customer needs. This involves resolving post-sales non-technical customer inquiries via phone and electronic means, as well as, technical questions regarding the use of and troubleshooting for our Electronic Support Services. A primary point of contact for customers, you are responsible for facilitating customer relationships with Support and providing advice and assistance to internal Oracle employees on diverse customer situations and escalated issues. Career Level - IC3 Responsibilities 6-10+ Years’ experience as an Oracle database engineer/DBA Extensive knowledge and solid troubleshooting experience in all areas of Oracle database technology. Advanced level skills in RAC, ASM, Performance tuning, HA, Backup and Recovery Experience in database upgrades, migrations, installations and patching Ability to quickly grasp complex technical issues Knowledge and experience in administration of engineered system products like Exadata and ZDLRA Experience in Engineered system Maximum Availability Architecture Clear understanding of Exadata features like Flash cache, Storage Index, HCC and IORM Understanding of Luns, Cell Disk and Grid disk Understanding Engineered system Health Check Exadata Full stack patching and Upgrade OEM 13c implementation & migration Skills in Golden Gate replication Day to day monitoring experience of RDBMS and RAC environment Willingness to work in shifts and on weekends Great problem-solving skills, with a strong bias for quality and engineering excellence at scale. Not only must you able to identify, analyse, diagnose, and troubleshoot complex problems using appropriate tools under constraints, but able to handle with utmost professionalism without compromising customers’ satisfaction. Will have strong customer-centricity mindset and the passion to work in Service Support line of business including to provide preventive support and proactive advice Excellent interpersonal communication and written skills in English Able to work with minimal supervision, self-motivated, self-directed and take initiative to collaborate and synthesis with members locally or globally across different geographical time zone Degree in Computer Science, Engineering, related field or equivalent. About Us As a world leader in cloud solutions, Oracle uses tomorrow’s technology to tackle today’s challenges. We’ve partnered with industry-leaders in almost every sector—and continue to thrive after 40+ years of change by operating with integrity. We know that true innovation starts when everyone is empowered to contribute. That’s why we’re committed to growing an inclusive workforce that promotes opportunities for all. Oracle careers open the door to global opportunities where work-life balance flourishes. We offer competitive benefits based on parity and consistency and support our people with flexible medical, life insurance, and retirement options. We also encourage employees to give back to their communities through our volunteer programs. We’re committed to including people with disabilities at all stages of the employment process. If you require accessibility assistance or accommodation for a disability at any point, let us know by emailing accommodation-request_mb@oracle.com or by calling +1 888 404 2494 in the United States. Oracle is an Equal Employment Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability and protected veterans’ status, or any other characteristic protected by law. Oracle will consider for employment qualified applicants with arrest and conviction records pursuant to applicable law.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior SoC Director / SoC Director Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for highly talented SoC Director for the following roles Senior Director / SoC Director of SOC is : Trust, loyalty, and ability to command Technical respect with foreign partners after having Taped out Successfully multiple chips to high volume production….this should be easily achieved under his/her belt !!!!!!!! Somebody we can trust to drive on the World stage without embarrassing us Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs. The ideal candidate will have expertise in digital design and RTL development, with a deep understanding of the design convergence cycle, including architecture, micro-architecture, synthesis, timing closure, and verification. Key Responsibilities: Proficiency in AI Accelerators DNN Accelerators co-processors Interconnect Fabric Cache Coherency D2D C2C SoC Director Bangalore We develop highly scalable and innovative AI accelerator chips that offer high performance, low energy, and customer ease of implementation for embedded Edge AI vision-based applications and real-time data processing. Company has working HW & SW for customer sampling, with production designs in the pipeline, and a system architecture designed a future of neuromorphic computing. We are backed by excellent VC funding and is currently in a stage of rapid growth. While our tech is one of a kind we would not be able to make these advancements without our team. Our collaborative culture is one of the keys to our success. Who You Are You are an open and honest communicator who values your team You are innovative, enjoy bringing new ideas to the table and are receptive to ideas and feedback from others You’re passionate about advancing the state of the world through new technology You enjoy the ambiguity and pace of a startup environment The role This leadership role will be responsible for the global VLSI efforts at and It is a highly visible role reporting to Senior Director with ownership of all pre/post Si activities, leading interface with external EDA, IP, Design Service partners, managing the and a global VLSI team. What you will be doing: Ownership of pre-Si Design of the next-gen AI accelerator at driving deliverables with Design and IP Service providers, CAD tools, IPs, DFT/PD/Packaging and Test. Work closely with internal Architecture, SW, Emulation, and system board designers on product definition, microarchitecture, and design implementation. Build and manage the VLSI team of front-end design and verification engineers across India and Taiwan. Establish best practices for development, testing, reviews, and documentation. Participate in strategic discussions for product features and roadmap. What we expect to see: BS/MS in Electrical/Electronic Engineering with 18+ years of experience in VLSI, SOC design, several Si tape-out/production. Hands-on experience in front-end design, VLSI flows, and working experience for all aspects of Si tape-out, post-Si validation. Self-driven, organized with strong leadership and communication skills. Experience in building and managing teams with the ability to motivate and lead in a startup environment. Proven track record in several successful productizations. What we would be happy to see: Knowledge of AI, specifically Deep Neural Networks Application-specific accelerators or co-processors Startup experience Hours: Full time /3 days office-onsite Employment Opportunity and Benefits of Employment: We are committed to creating and fostering a diverse and inclusive workplace environment for all of our employees. We are an equal opportunity employer. Contact: Uday Mulya Technologies Email: muday_bhaskar@yahoo.com

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

We're seeking an exceptional and seasoned Product Leader to join our dynamic team. As an early stage startup, we're at a pivotal growth stage, and this role offers a unique opportunity to define, launch, and scale innovative fintech products that will shape our future. You'll own significant product areas, drive strategy, collaborate closely with engineering and business teams, and ultimately deliver immense value to our users and the market. This is a high-impact role for someone who thrives in a fast-paced, ambiguous environment and wants to build world-class financial products. What You'll Do: Product Strategy & Vision: Define the long-term product vision and strategy for key product areas, aligning with overall company goals and market opportunities in the fintech space. Conduct market research, competitive analysis, and customer feedback synthesis to identify unmet needs and innovative solutions. Roadmap Ownership: Own and prioritize the product roadmap, making data-driven decisions on feature development, enhancements, and deprecations. Balance short-term tactical needs with long-term strategic objectives. Execution & Delivery: Lead the entire product lifecycle from ideation to launch and post-launch optimization. Work closely with engineering, design, and other stakeholders to translate product requirements into detailed specifications and user stories. Ensure timely and high-quality product releases. Cross-Functional Collaboration: Serve as the primary liaison between business, engineering, design, sales, marketing, and operations teams. Foster strong relationships and clear communication to drive alignment and efficient execution. Market & Customer Insight: Deeply understand our target users, their pain points, and needs within the fintech ecosystem. Stay abreast of industry trends, regulatory changes, and emerging technologies to ensure our products remain competitive and compliant. Performance & Growth: Define key product metrics and KPIs, rigorously track performance, and iterate based on data and user feedback. Identify opportunities for growth and monetization. What You'll Bring: Education: Bachelor's or Master's degree in Engineering, Computer Science, Business, or a related field from a Tier 1 institution. Experience: 8 to 12 years of progressive experience in product management roles, with a proven track record of successfully launching and scaling complex software products. Startup Acumen: Demonstrated experience working in a startup or early-stage environment (Series A/B preferred). You're comfortable with ambiguity, rapid iteration, and making impactful decisions with limited resources. Fintech Domain: Strong, demonstrable experience in the FinTech industry is essential. This includes deep understanding of areas like digital payments, lending, banking infrastructure, wealth tech, regtech, KYC/AML, fraud, or financial data platforms. Product Craftsmanship: Expertise in product discovery, user research, and validating product ideas. Proficiency in agile development methodologies and working closely with engineering teams. Strong analytical skills with the ability to use data to inform product decisions. Leadership & Communication: Exceptional leadership skills with the ability to influence cross-functional teams without direct authority. Outstanding written and verbal communication skills, capable of presenting complex ideas clearly to diverse audiences (internal and external stakeholders). Problem-Solving: A strategic thinker with a bias for action, capable of breaking down complex problems and driving practical solutions. Why Join? Shape the Future: Lead critical product initiatives that directly impact our growth and market position. High Impact: Your contributions will be central to our success and the innovation of financial services. Innovation: Work on cutting-edge financial technology and solve real-world problems. Culture: Join a vibrant, collaborative team that values innovation, continuous learning, and direct impact. Growth: Significant professional growth opportunities as the company scales rapidly. Competitive Compensation: Attractive salary, equity, and benefits package. If you are a visionary Product Leader passionate about fintech and eager to build groundbreaking products from the ground up, we encourage you to apply!

Alternate Job Titles: Senior Staff AI Methodology Engineer Principal EDA Solutions Engineer AI-Driven RTL-to-GDS Flow Specialist Lead Application Engineer – AI EDA Solutions We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way. Your leadership skills are proven—whether guiding junior engineers, collaborating with global customers, or interfacing with R&D to influence product direction. You communicate complex concepts with clarity, and your presentations inspire confidence and trust. Adaptable and resourceful, you excel at managing multiple priorities in dynamic, fast-paced environments. You have a track record of technical excellence, a commitment to continuous learning, and a genuine enthusiasm for empowering others. If you are driven by solving tomorrow’s silicon challenges and have a curiosity to explore new AI-driven design paradigms, you will find your next career milestone here at Synopsys. What You’ll Be Doing: Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries. Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs. Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation. Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges. Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables. Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement. The Impact You Will Have: Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results. Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development. Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation. Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market. Elevate the technical capabilities of the application engineering team through mentorship and cross-training. Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with10+ years of relevant experience. Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar). Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes. Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies. Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment. Outstanding verbal and written communication, presentation, and customer interaction skills. Who You Are: Collaborative and empathetic leader, skilled at building relationships and enabling the success of others. Analytical thinker with a problem-solving mindset and a passion for continuous improvement. Adaptable and resilient in the face of evolving customer requirements and technology landscapes. Strong organizational skills, able to manage multiple projects and priorities with poise. Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design. The Team You’ll Be A Part Of: You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

JOB DESCRIPTION Are you looking for an exciting opportunity to join a dynamic and growing team in a fast paced and challenging area? This is a unique opportunity for you to work in our team to partner with the Business to provide a comprehensive view. Role provides the ability to influence the strategic direction of J.P. Morgan’s Global Banking business by sharing new insights and driving thought leadership, as well as the ability to affect numerous aspects of a market-leading, global franchise. As a senior associate on the Strategy & Competitive Intelligence team, you will inform senior leaders, key partners, and sales force members about changes in the competitive landscape and the impact these changes have on our Global Banking business. In this role you will work on various recurring and ad hoc engagements that provide a deeper understanding of the competitive landscape so J.P. Morgan can compete most effectively. Competitive Intelligence is a dedicated function within J.P. Morgan’s Global Banking business, which includes Commercial Banking, Global Corporate Banking and Global Investment Banking. Recurring and project-based work will be relevant to Global Banking overall or one of the sub-businesses. The group is aligned with the Global Banking Business Intelligence team, which reports to the Global Banking CFO. The group maintains connectivity with Strategy & Competitive Intelligence teams throughout firm, sharing resources and best practices as needed. Job Responsibilities Develop deep understanding of the global banking landscape and activities taking place at peer banks, non-bank lenders, and boutique IBs - share insights with Global Banking leaders, partners and sales force Deliver insights into new trends impacting Global Banking by analysis and synthesis of competitor news articles, financial statements, presentations, industry reports and anecdotal input via recurring deliverables and ad-hoc projects Analyze the impact of competitors strategies and market trends on J.P. Morgan’s Global Banking strategy Leverage market share information to provide strategic updates to Global Banking leaders and partners in a timely manner Work independently and with teammates on ad-hoc projects / requests Engage with broader Global Business Intelligence team on internal activities (i.e. weekly meetings, brainstorming sessions, volunteer activities) Support broader team projects as needed Required qualifications, capabilities and skills Qualified graduate from tier 1 school with relevant experience 5-8 years of relevant experience in consulting, business management, strategy, finance, project management or related field Ability to synthesize large amounts of qualitative information and present concise, easy-to-read findings to an executive audience Superior writing and verbal communication skills; strong presentation skills Comfortable working with employees at various seniority levels and locations while building strong internal relationships Self-starter, ability to work both independently and as part of a team Experience in managing project teams along with multiple projects and timelines Preferred qualifications, capabilities and skills Experience in financial services industry ABOUT US JPMorganChase, one of the oldest financial institutions, offers innovative financial solutions to millions of consumers, small businesses and many of the world’s most prominent corporate, institutional and government clients under the J.P. Morgan and Chase brands. Our history spans over 200 years and today we are a leader in investment banking, consumer and small business banking, commercial banking, financial transaction processing and asset management. We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants’ and employees’ religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation. ABOUT THE TEAM J.P. Morgan’s Commercial & Investment Bank is a global leader across banking, markets, securities services and payments. Corporations, governments and institutions throughout the world entrust us with their business in more than 100 countries. The Commercial & Investment Bank provides strategic advice, raises capital, manages risk and extends liquidity in markets around the world.

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Description In your new role you will: Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design. Work independently in different phases of the RTL2GDS flow with focus on Synthesis and Constraining for efficient Timing Closure, Equivalence check, PnR closure, IR/EM analysis and fixing along with physical checks cleanup sign-off Work with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow. Focus on PPA, define the Partition shapes, pins and feedthrough along with IP integration guidelines are followed (reviewed along with IP owners) to suit the requirements. Analyze and solve problems of high complexity using your global expert network Drive the PnR closure of multimillion gate designs in lower technology nodes, perform SoC level IR/EM analysis, debugging and fixing. Running SoC level Physical verification, debugging and fixing including Chip finishing, metal fill, Sealring and Tapeout checks Be a member of an expert network and drive innovation, methodology for the RTL to GDS2 development cycle of next generation automotive SoCs. Your Profile You are best equipped for this task if you have: A degree in Electrical Engineering, Microelectronics or a similar field. At least 6 of experience in Physical Design of highly complex SoCs. Experience in RTL coding, IP issues and handling is plus. Programming skills and knowledge in scripting languages like Tcl, Perl or Python. Experience in working as a member of SoC design teams with high cost and quality awareness. Fluent English language skills – with German being an added plus. Understanding of industry standard tools for physical design and signoff Be a quick learner and team player while taking and acting on responsibilities Contact: Gowri Shenoy, LinkedIn #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Mission Set up, organize, and manage the project team, to ensure the process definition, the supply and development of industrial systems, specific or not, in compliance with QCDP targets and industrial performance. He leads the quality convergence and ensures the Product Conformity of his perimeter. He co-leads the relations with process and product engineering, with the project team and with the Production Department of the plant. Management Functional or hierarchical responsible of PFIs, CAMIs / Specialists and geometers within its scope (depending on shop and project context). He leads all persons contributing to the industrial system that he’s controlling. During the industrial phase, he leads the start-up team of his shop (Including, for example, AVES convergence...) Detailed Missions The Leader is nominated from the Concept Freeze and at the latest from the Vehicle Pre-Contract VPC up to Manufacturing Approval MA + 3 months Purpose Ensure The Process Design Of His Shop Its detailed feasibility, Compliance with Shop rules and standards, including consideration of PRs and NRL Its consistency with the technical definition Product and with other processes (ex: POI / POE assignment ...) Its ability to ensure compliance, Its optimum of economic performance and industrial exploitation, within the global optimum driven by CPE Considering feedback from recent projects and plant constraints. In This Context Propose Technical Definition (DT) changes if necessary Alert on his unmanageable difficulties in internal team Raise arbitrations whenever necessary, with its process counterparts and / or the IST (product design) Refer to CPE arbitration, in case of non-negotiable litigation at its level A - Planning and construction Establish The Project Schedule In Coherence With The Project Master Planning, The Shop Interfaces And The Standard Schedule Of The Shop (PRM), And Pilot Its Realization, In Particular Coordinate the planning of the activities and put it under control (co-signed internal and external schedules) Realize or manage the realization of the deliverables of his shop, ensuring a good distribution to all customers Pilot the implementation of the master plan, medium and long term, of the plant following shop policy Define the necessary changes in the serial process to prepare for the integration of the new vehicle and pilot the evolutions of the specific industrial facilities following the WANT TO BE of the plant B - Define targets and ensure convergence Build, With His Job And The CPE, The Targets Consistent With The Program Framework, The Best Practices Of His Department And The Objectives Of The Manufacturing, For Investments, associated costs (Engineering Entry Ticket, MAPU, start-up costs) industrial performance (for example according to trades: DST / DSTR, Veh / FTE, reliability, HSEE, DPU, IFA Yoka, Production Indirect Costs, yield ratio, functional rate, ...) Ensure coherence between Shop investment budget (BAI), and project objectives Manage the drafting of the specifications for RFQ and the dispatching of the lots Build scenarios of sourcing with the UFST and the Plant Formalize the commitments to the VPC and then to the Contract (Contributor to the writing of the Manufacturing Synthesis File, startup protocol, Shoki Ryudo ...), Write the CPI (investment project contract) for his scope and ensure its validation. Ensure the respect of the commitments (investments, Engineering Entry Ticket, Schedule, ...) Prepare and ensure technical and economic reporting in ad hoc meetings (QCDP, RAP, PPCM, RDU, Technical Committees, Performance Committees, IP and IP + ...) Prepare and validate the EQM, PPCM. C - Animation Manage Through His Dashboard The Progress Of The Activities And, The Convergence To The Commitments Of Quality And Performance Of The Means And To The Convergence Product / Process Conformity In Development Phase And In Launching Phase. Pilot The RPES / APES And Prepare The Milestone Reviews With The PFI And The Business. Ensure The Hierarchical / Functional Management (following Organization) Of His Team Project Lead The Process Team (UET And Functional Collaborators) By Ensuring The good estimation of resources and skills in collaboration with the ACRC of its department. Respect for the contractualized Engineering Entry Ticket The availability of the specialists in the correct timing Set Up And Animate The Necessary Meetings With His Team, His Internal Partners (RNTO, Supply Chain, In Plant Flow, Automatism, Maintenance, Building, HSEE ...) And Suppliers Of Equipment Goods, To Ensure the team spirit focus on the objectives set Ensure the synchronization and convergence of activities in accordance with the schedule and the required quality criteria Follow up the digital and physical validation plans and the control of results Lead product / process convergence and solve technical hard points, Submitting to arbitration of CPE the disagreement that cannot be handled at its level D - Start-up activities Manage the start-up, installation, development and reception of tooling, guaranteeing compliance with the specifications (including geometry for the concerned shops), the product quality obtained (Aspect, perceived quality, AVES ...) under the conditions of contractual performance, and deadlines Ensure transverse animation on its perimeter (to ensure convergence at the vehicle level: example AVES Montage, MAPU). In collaboration with the Plant Department, ensure the validation of the technical agreements and payment agreements of the installations when the conditions are fulfilled Manage the implementation of monitoring plans through the Compliance Convergence Plan and validate their content Ensure the transfer to production teams, with remains to be clearly identified if necessary Facilitate the production of project needs within his department (MAPU, PT ...) E-Physical project activities Manage the project activities at RNAIPL Chennai plant Co-ordinate the Industrialisation phase project activities from VC until MA for handover to the plant Manage the overall convergence of the poject with all necessary stake holders( Product, Manufacturing, Quality, Plant PE etc) Drive the Zone leaders/ Zone engineers for the timely closure of the concerns F - End of project Ensure the Hand over with the DIVD and the Plant on the remaining items of the project In collaboration with the ACRC and its department head, prepare and ensure the mobility of its employees at the end of the project (CUET role) Throughout the project, be the driving force of the business capitalization: best practices, evolution of standards, specifications, modes of operation, investments, RFNM ... through RETEX and with the profession Key Cooperation Department Heads / Shop Department / ACRC Chief Production Engineer - Chief Vehicle Engineer (CVE) and CVE Segment. Other CPM process, CPM facilities, IST product, Architects, PFE, PSV (Veh Synthesis Pilot). Industrial Strategy (DSI), Engineering Tooling and Support, Group Logistics Manufacturing Department (DFLG), After Sales Department DIPVE framing service and AVP team Experts organization (referent, leader …) Team of each process (stamping, assembly, painting & plastic injection, logistics, assembly, standard processes), and start-up team. Shop Quality Engineer (IQM) , Project Schedule Engineer (IPP) and Shop Schedule Engineer (IPM) Cost Synthesis Engineer - Management Control Direction - DPCII Analysts, Protos Project Manager Plant Department Chief (Manufacturing, Logistics, Quality, Maintenance...), Plant Project Leader, Plant Sector Leader, DIVD Purchasing Project Manager - Suppliers. USFT / USMT (Upstream Strategic Function / Material Team) HSEE (1 window person for each shop)

Job Description Are you looking for an exciting opportunity to join a dynamic and growing team in a fast paced and challenging area? This is a unique opportunity for you to work in the Transformation team to partner with the Business. Job Summary As a Business Analyst in the Transformation team, you'll promote structure and discipline around each initiative using standard project deliverables and framework. You'll establish scope, perform detailed business impact analysis in support of management decisions, and define roles and responsibilities. You'll also establish and document requirements, resolve resource/scheduling conflicts, and manage changes to project scope. Your role will include documenting and completing testing requirements, creating and managing implementation plans, and leading/participating in meetings at the operational and project level. You'll provide continuous feedback on project status and issues, serving as the overall escalation point to ensure the project tracks to original expectations. Job Responsibilities Project analysis, including documenting business requirements, detailing issues and risks, and drafting business processes and data flows Analyze data, including data collection, synthesis, and translation of results into concrete actionable solutions Identify gaps between applicable requirements and current procedures/controls and drive resolution of mitigating controls Work with business partners to design and implement enhancements to existing processes and/or business applications, introduce new processes and/or toolsets, and engage in process re-engineering Develop and implement solutions that strengthen business operating models, enhance the client experience, and improve efficiency and controls Define user acceptance test plans and test cases, coordinate and execute user acceptance testing and interpret, assess, and communicate results to enable signoff on deliverables Provide implementation support, inclusive of testing and process change management, and ensure those implementations meet requirements established by Oversight and Control partners Apply a critical eye in evaluating existing processes and frameworks; challenge the status quo and recommend solutions / enhancements to operating models and controls Required Qualifications, Capabilities, And Skills Minimum 1 year business analysis experience Bachelor’s degree required Excellent communication and presentations skills across various stakeholders and senior management Intermediate/Advanced experience using Microsoft Office, including Excel, Visio and PowerPoint Excellent analytical and logical thinking to understand and analyze complex business processes Strong organizational and prioritization skills, detail-oriented and strong interpersonal skills Ability to analyze and resolve project-related issues and follow through with set objectives Ability to deal with different stakeholder groups to elicit business requirements, procedures, and processes Ability to work in a high paced environment, be flexible, follow tight deadlines, organize and prioritize work Be a team player who shows commitment and dedication, and can maintain a positive attitude and high-level of performance on high-profile/time-sensitive initiatives ABOUT US JPMorganChase, one of the oldest financial institutions, offers innovative financial solutions to millions of consumers, small businesses and many of the world’s most prominent corporate, institutional and government clients under the J.P. Morgan and Chase brands. Our history spans over 200 years and today we are a leader in investment banking, consumer and small business banking, commercial banking, financial transaction processing and asset management. We recognize that our people are our strength and the diverse talents they bring to our global workforce are directly linked to our success. We are an equal opportunity employer and place a high value on diversity and inclusion at our company. We do not discriminate on the basis of any protected attribute, including race, religion, color, national origin, gender, sexual orientation, gender identity, gender expression, age, marital or veteran status, pregnancy or disability, or any other basis protected under applicable law. We also make reasonable accommodations for applicants’ and employees’ religious practices and beliefs, as well as mental health or physical disability needs. Visit our FAQs for more information about requesting an accommodation. About The Team J.P. Morgan’s Commercial & Investment Bank is a global leader across banking, markets, securities services and payments. Corporations, governments and institutions throughout the world entrust us with their business in more than 100 countries. The Commercial & Investment Bank provides strategic advice, raises capital, manages risk and extends liquidity in markets around the world.

Job Description Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues Conduct thorough design reviews and provide constructive feedback to peers and junior engineers Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA Support Low Power Implementation Support formality checks Preferred Experience Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC Experience in owning or supporting STA at full-chip level Exposure to latest methodologies in constraints generation, promotion/demotion and validation Familiarity with Low Power Implementation flows Qualifications Required and Preferred Qualifications Required: Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Ability to mentor and guide junior engineers in IC design best practices and methodologies Scripting experience in Shell, Perl, Python and TCL is a plus Good communication skills for interacting between different design groups cross functional groups are required Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Some level of understanding of DFT flows and steps Exposure to Automotive SoC designs Additional Information Soft Skills and Cultural Fit Exceptional problem-solving skills with the ability to analyse complex design challenges Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required: Bachelor's degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints Additional Information Soft Skills and Cultural Fit Strong communication skills to articulate design concepts and collaborate with multi-disciplinary teams Proactive attitude with a commitment to continuous learning and professional development A collaborative mindset with the ability to thrive in a fast-paced, dynamic environment Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Conduct organic synthesis and chemical reactions as per R&D protocols. Perform purification, extraction, recrystallization, and characterization of organic compounds. Maintain lab records, chemical inventories, and ensure safety protocols. Assist senior scientists in process development and scale-up. Operate analytical instruments like HPLC, GC, IR, and NMR (basic knowledge acceptable). Support quality control and documentation work. Ensure compliance with standard operating procedures (SOPs). trong knowledge of organic chemistry and reaction mechanisms Basic handling of laboratory instruments Good documentation and reporting skills Ability to work in a team and follow instructions Attention to detail and safety-conscious approach Job Types: Full-time, Permanent Pay: ₹18,000.00 - ₹20,000.00 per month Benefits: Health insurance Provident Fund Schedule: Day shift Education: Master's (Preferred) Experience: Quality control: 1 year (Preferred) Research & development: 1 year (Preferred) Location: Hyderabad, Telangana (Preferred) Work Location: In person Application Deadline: 15/07/2025

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Design Responsibilities Architecture exploration Micro-architecture development Soft and hard IP identification, selection and integration Collaboration with verification and emulation teams in test plan development and debug Collaboration with implementation team to close the design on timing and power Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) Development Experience in one of these skills: Micro-architecture and RTL development for complex control and data path IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development Experience with Verilog or System Verilog Lint, CDC (Clock Domain Crossing), Synthesis and Power Optimization Preferred Qualifications 15+ years of experience in silicon development Experience in data path development Experience in CPU, NOC (Network on Chip), Memory and Peripheral Subsystems Experience in HLS (High-Level Synthesis) Experience with Synthesis, Timing Closure and Formal Verification Methodology Experience with Power Analysis and Optimization Experience with scripting languages (TCL, Python, Perl, Shell-scripting) Experience working across multiple projects About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.