2263 Synthesis Jobs - Page 31

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 5+ years of experience in STA/Timing from product-based companies. Job : STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS ICC, Innovous , PT/Tempus Familiar with process technology enablementCircuit simulations using Hspice/FineSim, Monte Carlo.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience 7 to 15 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS ScriptingTCL, Perl

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 2+ years Hardware Engineering experience or related work experience. 2+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Associate's degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Additional Job Role Work on Logic & Physical aware Synthesis with Low Power, QoR optimization and Netlist Signoff flows. Work on Logic equivalence check and low power check clean up. Work on constraints development by interacting with designers and help in porting constraints from block to top-level. Should be able to handle multiple projects by leading a team of 3 to 5 members and deliver. Should be able to lead implementation flow development effort independently by working closely with design team and EDA vendors. Should be able to drive new tool evaluation, methodology refinement for PPA optimization. Should be sincere, dedicated and willing to take up new challenges. Skill Set Proficiency in Python/Tcl. Familiar with Synthesis tools (Fusion Compiler/Genus). Fair knowledge in LEC, LP signoff tools. Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management 3+ years with MTech or BTech with Hardware Engineering or related work experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Key Technical skills requirement: Candidate should have deep and sound understating of: Memory basic design understating for different architectures Memory measurement parameters Memory timing/power characterization and compiler engine building with all accuracy parameters involved Memory power views All the LVF/different forms of variation parameter Memory lib w.r.t. parameters/arcs/SDF conditions/variation parameters/QA steps/different formats Different Simulator tools Should have thorough understanding of release process to customers Knowledge of scripting languages such as Shell, Perl Good working knowledge of MS excel, PPT Mentoring skills to Juniors

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Additional General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 5+ years Hardware Engineering experience or related work experience. 5+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications 8+ years Hardware Engineering experience or related work experience. 8+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary PNR implementation for Qualcomm Hexagon DSP IP's 8+ years of experience in Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 5 to 10 years of experience in static timing analysis, constraints and other physical implementation aspects Minimum Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 2- 5 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum of 3+ years’ experience in the area of DFT-, ATPG, Scan Insertion, MBIST, JTAG -In depth knowledge of DFT concepts. -In depth knowledge and hands on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. -Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc. -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors. -Knowledge of equivalence check and RTL lint tool (like spyglass). -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem-solving skills

Terms of Reference (TOR) Strategy Development Consultant – Fairtrade NAPP Strategy 2026–2028 Subject: Consultant – NAPP Strategy 2026–2028 1. Who We Are The Constitution of Fairtrade NAPP was established in 2014. The organization is a member of Fairtrade International (www.fairtrade.net). Producer Networks (PNs) are regional associations that Fairtrade certified producer organizations may join if they wish. They represent small-scale producers, workers and other producer stakeholders. Fairtrade NAPP supports and empowers Fairtrade certified farmers and workers across the Asia Pacific region. The producers share 50% ownership of the Fairtrade system and have an equal voice in all decisions that affect them. As a Producer Network, NAPP ensures their voice is heard in the system. Currently NAPP has 276 Producer Organizations across 21 countries in Asia and Pacific Region supporting more than 260000 farmers and workers. NAPP’s mission is to facilitate the incorporation of more producers to be able to join the Fairtrade movement in Asia and the Pacific through an existing wide range of products and services. For more information please visit: www.fairtradenapp.org.Currently NAPP is working in 21 countries and supporting 15+ product categories through numerous services to the producer organizations. 2. Background and Context NAPP’s current strategic plan concludes in 2025. As we prepare for the next phase, NAPP seeks to develop a robust, inclusive, and forward-looking 2026–2028 Strategic Plan . The activity is co-funded by the European Commission Funding Framework Partnership Agreement (EC FFPA) program. The EC FFPA is strategic partnership program, which aims to strengthen Fairtrade as a representative, member -based regional, EU and global Civil Society umbrella organization, giving voice and empowering over 1900 Fairtrade Producer Organizations globally. Within this program, NAPP is developing its strategy to address the evolving needs of Fairtrade producers in the region, align with global Fairtrade directions, and reflect emerging trends in trade justice, sustainability, and producer resilience. Summary of the NAPP Strategy 2021–2025 The 2021–2025 strategy— “Doing Business with a Conscience” —was built around seven sustainability-focused service categories: Sustainable Livelihoods – Gender-inclusive value chains, decent livelihoods, crop diversification, and value addition. Sustainable Communities – Youth engagement, women’s empowerment, and localized entrepreneurship. Sustainable Trade – Market expansion, quality improvements, business resilience. Sustainable Technology – Digital traceability, smart tech for agri-practices. Sustainable Collaborations – Strategic partnerships and advocacy to promote domestic and ethical markets. Sustainable Environment – Circular economy models, climate adaptation pilots. Sustainable Fairtrade System – Stronger country networks, compliant governance, certification+ services. The strategy emphasized transparency, resilience, innovation, and the transformation of Fairtrade from niche to mainstream—while confronting introspective questions about cost competitiveness, trust, relevance, and the future role of certification. 3. Purpose of the Consultancy To support NAPP in developing its 2026–2028 Strategic Plan through a participatory, evidence- informed, and regionally grounded approach that aligns with global Fairtrade priorities while addressing unique challenges and opportunities in Asia-Pacific. This strategy will serve as a roadmap, ensuring that FT NAPP’s goals and activities are in sync with the development global Fairtrade System while reflecting the unique opportunities and challenges within the Asia and Pacific context. 4. Objectives of the Assignment Assessment of current strategy : Conduct strategic reviews and assess performance under the 2021–25 framework. Facilitate Strategic Planning: Lead the design and facilitation of the strategic planning process, integrating internal evaluations, market and policy trends, and Fairtrade global system priorities and Identify emerging priorities Stakeholder Engagement: Coordinate inclusive consultations with producer organizations, staff, Board members, and partners to gather strategic inputs. Draft Strategic Documents: Translate stakeholder insights and analyses into a comprehensive and actionable strategic framework for 2026-28 Support Communication: Help develop communication materials (e.g. summary documents and presentations) to share the strategy with internal and external stakeholders. 5. Scope of Work The consultant will be responsible for: Conducting a review of the current (2021–2025) strategy , lessons learned, and organizational performance. Leading internal and external stakeholder consultations , including country/regional teams and thematic advisors (e.g. gender, youth, climate, HREDD, LI/LW). Consultation with FT NAPP Board to align the strategic mission with Board’s vision. Coordinating focus groups or surveys with producer organizations across various countries to ensure inclusiveness. Drafting the 2026–2028 Strategy Document , including: Vision, mission, and values review (if needed) Strategic pillars and objectives Theory of Change or results framework Key implementation directions Preparing a PowerPoint summary and 2-page strategy brief for communication use. 6. Deliverables Inception Report (work plan, methodology) – Week 2 Stakeholder Consultation Summary – Week 6 Draft Strategy Document – Week 9 Final Strategy Document and Summary – Week 12 Strategic Presentation (PPT) – Week 12 7. Duration of the Assignment The consultancy will span three months (12 weeks) from the date of contract signing. Detailed timelines and milestones will be finalized during the inception phase. 8. Required Qualifications The ideal Consultant or Consultancy Firm should possess the following qualifications and experience: Strategic Planning Expertise : Proven experience in strategic planning for organizations with a regional presence and international affiliation. Familiarity with the Fairtrade system and experience working with diverse international stakeholders or certification schemes is highly desirable, alongside a strong understanding of the Asian context. Sector Expertise: In-depth knowledge of agriculture, smallholder farmer and worker support, sustainability, and sustainable development. Expertise in thematic areas under review and experience with delivering similar assignments are advantageous. Innovation and Methodological Proficiency : Demonstrated ability to propose innovative solutions and familiarity with relevant strategic frameworks and methodologies, such as SWOT, PESTEL, and Theory of Change. Facilitation and Engagement Skills : Strong facilitation skills and the ability to engage effectively with a broad range of stakeholders, including producers, board members, staff, and partners (regional and International). Analytical and Synthesis Skills : Proven ability to conduct stakeholder consultations, synthesize complex inputs, and translate them into coherent, actionable strategic documents Communication Skills : Excellent written and verbal communication skills in English, including the capacity to present ideas clearly and effectively to diverse audiences. 9. Application Process Interested consultants/firms are requested to submit the following: Technical proposal (max 5 pages) including methodology, timeline, and team composition List of deliverables along with the timeline CV(s) of consultant(s) highlighting relevant experience Financial proposal with clear cost breakdown Declaration of relationships – describe if your organization/employees have any business or personal relationships connected to NAPP; Two previous reports/documents on similar project/line to be submitted. Two recent references for similar work *Budget: The budget available for the assignment is 6000 Euro only inclusive of all cost. *Payment Terms: The payment terms for the assignment shall be 25% upon submission of inception report and 75% upon submission and approval of strategy document & other deliverables *Deadline for Submission: [19.07.2025] *Send Proposals to: hr@fairtradenapp.org

Job Purpose - Electronic Laboratory Notebook administration. - Literature survey. - Supervision of laboratory operation. - Ensuring laboratory safety and compliance. Job Responsibilities - Lead electronic laboratory notebook (ELN) software administration and management. Provide ELN traninigs to new joinees. Connect with third party and internal stakeholders on regular basis for implementation and troubleshooting. - Literature survey as per order forms. - Supervision of experimental work in laboratory. - Ensure laboratory safety and compliances - Ensure availability of raw materials and equipment required for the execution of experimental planning - Understand the safety aspects of all reactions and chemicals to be used in laboratory - Play the role of ERT and shift incharge - Perform night duties as per site philosophy -To ensure 100% compliance on ERA and zero safety incidents in lab - Laboratory management: disposal of samples, disposal of chemical waste, chemical inventory - Equipment maintenance: ensure PM of allocated instruments and inventory of spares - Chemdraw Scifinder, Reaxys, Orbit Patent and research article reading habit Strong chemistry background Synthesis chemistry

We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer. RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop C testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience

Key Responsibilities: Extract, clean, and analyze large datasets to identify patterns and trends. Develop and maintain dashboards and reports to monitor business performance. Work with cross-functional teams to improve data accuracy and accessibility. Drive data strategy, customer segmentation, and portfolio risk analysis. Contribute to AI-driven product innovations. Required skills & Qualifications: Education: Bachelor's or Master’s degree in Data Science, Statistics, Mathematics, Economics, Computer Science, or a related field. Proficiency in Python for statistical modeling, and exploratory data analysis, with hands-on experience in libraries such as Pandas, NumPy, Matplotlib, Seaborn, and scikit-learn. Expert-level SQL capabilities for querying relational databases and performing data extraction and transformation. Exposure to Tableau for developing dashboards and generating business insights. Strong analytical thinking, with a focus on problem synthesis, root cause analysis, and data storytelling. Experience with machine learning, deep learning, and natural language processing (NLP) is preferred. Strong communication and storytelling skills.

EXPERIENCE: 7 - 9 years of work experience in either credit/risk verticals of domestic private banks/ NBFCs/ Credit funds with focus on Corporate lending (Non-Real estate) Experience in financial modelling, valuation, industry/company research, use of financial databases like Bloomberg/CapitalIQ etc. Experience in creating presentations (e.g., industry primers etc.) Strong written (emails, presentations) and oral communication skills Prior exposure to diverse sectors (Steel, cement, capital goods, power etc.) would be an advantage. Qualifications: MBA from Top Tier Institutes/CA/CFA KEY RESPONSIBILITIES: Credit Risk & Structuring The incumbent will be part of the risk team and responsible for Credit Risk & Structuring for Corporate lending book across diverse sectors such that it aligns with the broader risk appetite and objectives of the group Financial modelling: Building financial models to assess deal attractiveness, alternate deal constructs and scenario analysis. Crisply articulate insights gained from these analyses and implications on the deal attractiveness/deal structure etc. Deal structuring: Develop excel models to assess and quantify impact of various deal structures. Company/sector research: As part of the deal evaluation process, compile and analyse relevant data on the sector, company, competitors etc. from databases, annual reports, expert conversations etc. Synthesis key messages from such research and conversations, and share with the Committee Due diligence: Effectively diligence companies and sectors through data, client meetings, site visits etc. Creating presentations: Creating portfolio presentations for Senior management Post deal involvement: Monitoring portfolio companies, active approach in anticipating challenges for the companies due to sector related changes

Line of Service Advisory Industry/Sector GPS X-Sector Specialism Operations Management Level Senior Associate Job Description & Summary At PwC, our people in software and product innovation focus on developing cutting-edge software solutions and driving product innovation to meet the evolving needs of clients. These individuals combine technical experience with creative thinking to deliver innovative software products and solutions. In business analysis at PwC, you will focus on analysing and interpreting data to provide strategic insights and recommendations for improving business performance. Your work will involve strong analytical skills and the ability to effectively communicate findings to stakeholders. *Why PWC At PwC, you will be part of a vibrant community of solvers that leads with trust and creates distinctive outcomes for our clients and communities. This purpose-led and values-driven work, powered by technology in an environment that drives innovation, will enable you to make a tangible impact in the real world. We reward your contributions, support your wellbeing, and offer inclusive benefits, flexibility programmes and mentorship that will help you thrive in work and life. Together, we grow, learn, care, collaborate, and create a future of infinite experiences for each other. Learn more about us . At PwC, we believe in providing equal employment opportunities, without any discrimination on the grounds of gender, ethnic background, age, disability, marital status, sexual orientation, pregnancy, gender identity or expression, religion or other beliefs, perceived differences and status protected by law. We strive to create an environment where each one of our people can bring their true selves and contribute to their personal growth and the firm’s growth. To enable this, we have zero tolerance for any discrimination and harassment based on the above considerations. Job Description & Summary: At PwC, our purpose is to build trust in society and solve important problems. We’re a network of firms in 157 countries with more than 300,000 people who are committed to delivering quality in Assurance, Advisory and Tax services. Within Advisory, PwC has a large team that focus on transformation in Government through Digital inclusion. The open position is for a candidate who desires to work with government clients and bring about a change in society. A successful candidate will be expected to work pro-actively and effectively on multiple client engagements over the period of time and take ownership of the entire project delivery he/she entrusted with. Responsibilities: · Lead the design and implementation of AI/ML models, particularly in the areas of Generative AI and advanced data analytics · Develop and fine-tune large language models (LLMs) and transformer-based architectures for specific use cases · Collaborate with data engineers, product owners and business stakeholders to translate requirements into intelligent solutions · Deploy ML models in production using MLOps practices, ensuring scalability and performance · Drive experimentation with cutting-edge Gen AI techniques (e.g., text generation, summarization, image synthesis) · Conduct data exploration, feature engineering and statistical modeling to support various business needs · Mentor junior team members and guide them in model development and evaluation best practices · Stay up to date with the latest research and industry trends in AI, ML and Gen AI · Document methodologies, models and workflows for knowledge sharing and reuse Mandatory skill sets: · 4+ years of experience in AI/ML and data science, with proven experience in Generative AI · Hands-on expertise with Python and relevant ML/AI libraries (e.g., PyTorch, TensorFlow, Hugging Face, Scikit-learn) · Strong understanding of LLMs (e.g., GPT, BERT, T5), transformers and prompt engineering · Experience with NLP techniques such as text classification, summarization, entity recognition and conversational AI · Ability to build and evaluate supervised and unsupervised learning models · Proficient in data wrangling, exploratory data analysis and statistical techniques · Familiarity with model deployment tools and platforms (Docker, FastAPI, MLflow, AWS/GCP/Azure ML services) · Excellent problem-solving, analytical thinking and communication skills Preferred skill sets : · Experience fine-tuning open-source LLMs using domain-specific data · Exposure to reinforcement learning (RLHF), diffusion models or multimodal AI · Familiarity with vector databases (e.g., FAISS, Pinecone) and retrieval-augmented generation (RAG) architectures · Experience with ML pipelines and automation (CI/CD for ML, Kubeflow, Airflow) · Background in conversational AI, chatbots or virtual assistants · Knowledge of data privacy, ethical AI and explainable AI principles · Publications, Kaggle participation or open-source contributions in the AI/ML space Years of experience required: 4+ years Education qualification : · Bachelor’s or Master’s degree in Computer Science, Artificial Intelligence, Data Science, Statistics or a related field Education (if blank, degree and/or field of study not specified) Degrees/Field of Study required: Bachelor Degree, Master Degree Degrees/Field of Study preferred: Certifications (if blank, certifications not specified) Required Skills Artificial Intelligence Markup Language, PyTorch, Scikit-Learn, Tensorflow Optional Skills Accepting Feedback, Accepting Feedback, Active Listening, Analytical Thinking, Business Administration, Business Analysis, Business Case Development, Business Data Analytics, Business Process Analysis, Business Process Modeling, Business Process Re-Engineering (BPR), Business Requirements Analysis, Business Systems, Communication, Competitive Analysis, Creativity, Embracing Change, Emotional Regulation, Empathy, Feasibility Studies, Functional Specification, Inclusion, Intellectual Curiosity, IT Project Lifecycle, Learning Agility {+ 19 more} Desired Languages (If blank, desired languages not specified) Travel Requirements Not Specified Available for Work Visa Sponsorship? No Government Clearance Required? No Job Posting End Date

Job Requirements Key Responsibilities: Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production. Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets. Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness. Define and implement test strategies for analog and mixed-signal IPs , including DFT hooks, wrappers, and test mode integration. Create test patterns and perform ATPG analysis to ensure test coverage goals are met. Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams. Automate and optimize DFT flows and scripting for scalability and efficiency. Required Qualifications: B.E./B.Tech or M.E./M.Tech in Electrical Engineering or related discipline. Minimum 10 years of hands-on experience in DFT with successful tapeouts. Strong knowledge of scan insertion , scan compression , transition fault (at-speed) testing , and boundary scan (IEEE 1149.1/1500). Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired. Experience with ATPG tools , test coverage analysis, and test pattern generation. Solid understanding of DFT for AMS blocks , including challenges in testability of analog circuits. Familiarity with scripting languages (TCL, Perl, Python) for automation. Good understanding of STA constraints for DFT and impact on synthesis and physical design. Proven experience in silicon debug and production test support Work Experience Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired. Experience with ATPG tools , test coverage analysis, and test pattern generation. Solid understanding of DFT for AMS blocks , including challenges in testability of analog circuits. Familiarity with scripting languages (TCL, Perl, Python) for automation. Good understanding of STA constraints for DFT and impact on synthesis and physical design.

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Bachelor’s or Master’s degree in Electronics 4–8 years of hands-on experience in VLSI DFT Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Experience with silicon bring-up and production test support Excellent problem-solving and debugging skills Strong communication and teamwork abilities Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Experience in low-power DFT techniques Familiarity with scripting (Perl, Python, Tcl) for automation Good understanding of RTL design, synthesis, and timing closure

Job Requirements Define and implement DFT architecture and strategy for complex SoCs and ASICs Insert and verify scan chains, MBIST, LBIST, boundary scan (JTAG), and other test structures Develop and maintain ATPG (Automatic Test Pattern Generation) patterns and flows Work closely with RTL designers, verification teams, and physical design teams to ensure DFT requirements are met Debug DFT-related issues during simulation, emulation, and silicon bring-up Perform timing analysis and constraints development for DFT logic Drive silicon validation and yield improvement initiatives related to DFT Document DFT design and verification methodology Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities Work Experience Strong expertise in scan insertion, ATPG, MBIST/LBIST, and JTAG implementation Proficiency with DFT tools (Synopsys DFT Compiler, Tetramax, Cadence Modus, Mentor Tessent, etc.) Good understanding of RTL design, synthesis, and timing closure Knowledge of safety-critical or automotive DFT requirements (ISO 26262) Familiarity with scripting (Perl, Python, Tcl) for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities