Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team. We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Show more Show less

Company: Invengic @ Research Park, IIT Gandhinagar, Gujarat Duration: 12 Months Stipend: ₹6,000 – ₹10,000/month (potential full-time co-founder/lead role) Joining: Immediate (within a week) Are you a builder, a thinker, and a doer who dreams of launching impactful products and technologies? We are inviting applications for our Entrepreneur in Residency (EIR) Program — a unique opportunity to work hands-on with cutting-edge technologies, fast-prototype real-world solutions, and grow into a leadership or co-founding role. 🌟 Who We’re Looking For We’re hiring for two tracks under the EIR program: 🛠️ Track 1: Embedded Systems & Robotics Innovation Preferred Background: Mechatronics, Electrical, Electronics, Instrumentation, Robotics Required Skills: Hands-on experience with microcontrollers like Arduino, Raspberry Pi, ESP32 Familiarity with sensor and actuator integration, analog/digital circuitry Knowledge of embedded systems and real-time data processing Programming in Python and/or C++ Experience with ROS/ROS2, Gazebo, RViz is a big plus Clean, modular, and documented coding habits Bonus: CAD proficiency (SolidWorks/Fusion 360/Inventor) Experience with 3D printing, mechanical prototyping, or product development 🧪 Track 2: Materials, Membranes & Environmental Innovation Preferred Background: Chemical Engineering, Materials Science, Nanotechnology Required Skills: Interest/experience in air purification, filtration systems, or membranes Understanding of nanomaterials, polymeric/ceramic composites, or synthesis techniques Familiarity with material characterization methods Ability to translate lab research into field-ready products Bonus: Exposure to startup R&D workflows Interest in sustainable technology, health-tech, or clean-tech commercialization 🎁 What You’ll Get Hands-on entrepreneurial experience in a deep-tech startup environment Mentorship from seasoned professionals in R&D and business Ownership of mini-projects with potential to scale into real products Direct impact on innovations like the Falcon Arm, filtration membranes & more Certificate of Completion with recommendation letters based on performance Possibility of full-time offer, co-founder role, or venture incubation 📩 To Apply Send your resume to: team@coprotectventure.in Or WhatsApp at: 8511149747 🌐 Visit: www.coprotectventure.in This is your chance to invent the future , not just observe it. If you’re hungry to learn, build, and create — this EIR program is made for you. Show more Show less

Site Name: India - Karnataka - Bengaluru Posted Date: May 26 2025 GDC Sourcing Manager Responsibilities: The GDC Sourcing Manager will be responsible for the delivery of the critical Source to Contract service for one or multiple regions across Indirect Categories such as IT, Marketing, Professional & Corporate Services. This role will collaborate with the procurement category and local market teams (LOC) to deliver sourcing, negotiation, contract execution, and supplier lifecycle management services to the global procurement organization. This service is a cornerstone of the future procurement operating model and will enable the function to industrialize its core operation, driving best practice, providing practical knowledge for development of best-in-class category strategies, consistency of execution, and continual improvement. The role is also accountable for the transition to, and ongoing delivery of, the future ready procurement operation model, for assigned geographies, as it relates to the GDC. As such the role is pivotal to the successful execution of the procurement future ready transformation Strategy execution Execute sourcing strategies for spend categories in scope of responsibility aligned with the requirements of stakeholders and business partnering with Global Category team. o Deliver benefits identified in strategies, local, regional and global, through effective and collaborative strategy execution, aligned to assurance of supply (risk management), quality, service, cost and innovation. o To ensure GSK’s Procurement policies, procedures, processes, systems and methodologies are utilized in a compliant manner in the area of responsibility. Benefit delivery Support category leads in the creation and delivery of effective savings targets agreed with key stakeholders and Finance in accordance with the agreed Savings Methodology. o Deliver benefit identified in strategies, local, regional and global, through effective and collaborative strategy execution, aligned to assurance of supply (risk management), quality, service, cost and innovation. o Deliver savings and other set KPIs critical to global procurement plans as aligned with key stakeholders and Finance in accordance with the Savings Methodology and global budgets. Business partnering & stakeholder management in GSK Collaborate with key stakeholders to deploy strategies globally/regionally, facilitated by robust implementation and transition plans. o Demonstrated success in collaboration with a wide range of senior leaders across [business areas] and supplier. o Resolve escalations, including from senior business stakeholders, timely and tactfully. o Understand and efficiently navigate organizational complexity to deliver set goals. We are looking for a Sourcing Manager and if you have these skills, we would like to speak to you. 9-10 years of relevant experience This role should have strong demonstrated procurement expertise in commercial and contract negotiations, strategic sourcing, Indirect category management, cost model synthesis and supplier relationship management for delivering multi-country, high spend complex engagements. Demonstrated experience in navigating through organizational complexity, collaborating simultaneously with multiple teams, influencing without authority, handling escalations and associated business impact. Demonstrated experience in understanding and utilising complex business processes in all GSK supplier transactions, including all risk/regulatory/compliance. Strong experience in using tools like Ariba or other equivalent sourcing execution technology. Why GSK? Our values and expectations are at the heart of everything we do and form an important part of our culture. These include Patient focus, Transparency, Respect, Integrity along with Courage, Accountability, Development, and Teamwork. As GSK focuses on our values and expectations and a culture of innovation, performance and trust, the successful candidate will demonstrate the following capabilities. Inclusion at GSK: As an employer committed to Inclusion, we encourage you to reach out if you need any adjustments during the recruitment process. Please contact our Recruitment Team at IN.recruitment-adjustments@gsk.com to discuss your needs. Why GSK? Uniting science, technology and talent to get ahead of disease together. GSK is a global biopharma company with a special purpose – to unite science, technology and talent to get ahead of disease together – so we can positively impact the health of billions of people and deliver stronger, more sustainable shareholder returns – as an organisation where people can thrive. We prevent and treat disease with vaccines, specialty and general medicines. We focus on the science of the immune system and the use of new platform and data technologies, investing in four core therapeutic areas (infectious diseases, HIV, respiratory/ immunology and oncology). Our success absolutely depends on our people. While getting ahead of disease together is about our ambition for patients and shareholders, it’s also about making GSK a place where people can thrive. We want GSK to be a place where people feel inspired, encouraged and challenged to be the best they can be. A place where they can be themselves – feeling welcome, valued, and included. Where they can keep growing and look after their wellbeing. So, if you share our ambition, join us at this exciting moment in our journey to get Ahead Together. Important notice to Employment businesses/ Agencies GSK does not accept referrals from employment businesses and/or employment agencies in respect of the vacancies posted on this site. All employment businesses/agencies are required to contact GSK's commercial and general procurement/human resources department to obtain prior written authorization before referring any candidates to GSK. The obtaining of prior written authorization is a condition precedent to any agreement (verbal or written) between the employment business/ agency and GSK. In the absence of such written authorization being obtained any actions undertaken by the employment business/agency shall be deemed to have been performed without the consent or contractual agreement of GSK. GSK shall therefore not be liable for any fees arising from such actions or any fees arising from any referrals by employment businesses/agencies in respect of the vacancies posted on this site. It has come to our attention that the names of GlaxoSmithKline or GSK or our group companies are being used in connection with bogus job advertisements or through unsolicited emails asking candidates to make some payments for recruitment opportunities and interview. Please be advised that such advertisements and emails are not connected with the GlaxoSmithKline group in any way. GlaxoSmithKline does not charge any fee whatsoever for recruitment process. Please do not make payments to any individuals / entities in connection with recruitment with any GlaxoSmithKline (or GSK) group company at any worldwide location. Even if they claim that the money is refundable. If you come across unsolicited email from email addresses not ending in gsk.com or job advertisements which state that you should contact an email address that does not end in “gsk.com”, you should disregard the same and inform us by emailing askus@gsk.com, so that we can confirm to you if the job is genuine. Show more Show less

Overview Of The Role As a member of the Enterprise Insights team at Target in India, you will expand efforts to help shape the ideal guest (consumer) experience and drive business and communication strategies and activations. This role supports the Category Insights team, which focuses on understanding consumer behaviors, attitudes, needs, and motivations across Target’s core businesses. You will play a key role in bridging the gap between business and guests through research by collaborating with multiple stakeholders including merchandisers, marketers, category managers, and creative teams. You will be responsible for designing and executing guest or consumer research to support key initiatives. You will be the primary contact for internal partners and will identify the appropriate research method, data source and vendor/supplier to execute work. Target leverages both qualitative and quantitative techniques and various secondary and proprietary sources of data to conduct research studies. As an advocate for the guest, you’ll be expected to frame findings into compelling insights and stories to establish guest understanding and empathy on the team and drive effective changes. Your work will have to include actionable recommendations for teams to then run with and achieve desired business goals for the organization. As a Sr. Marketing Researcher of Category Insights, you will report to the Sr. Manager, Insights and have responsibility for a Merchandise Pyramid. Responsibilities Identify best method or mix of methods for the research plan, timeline and resourcing. Work closely with cross-functional teams to identify and develop research plan based on analysis of knowledge gaps, project goals and risks. Conduct consumer research and report findings. Perform thorough qualitative/quantitative analysis to create meaningful insights and actionable recommendations. Work on an iterative approach through close alignment with business teams to influence impact of the project. Skills Ability to operate using a range of quantitative survey methods and techniques, qualitative methods/techniques, ethnographic and anthropological research, statistical testing within quantitative methods, sampling, and data analysis and synthesis across methods Solve business problems with a consumer- centered approach. Strong grasp of quantitative data analysis and statistics from a business perspective, including generating and distilling reports from syndicated and secondary sources Conducting field research (both quantitative and qualitative), including preparing survey design/ discussion guides etc. Strong collaboration to effectively influence a diverse set of stakeholders. Communicate complex concepts clearly and persuasively across different audiences and varying levels of the organization. Manage ambiguity, work autonomously, meet deadlines and multi-task in an agile environment. Preferred Background Four-year degree or equivalent experience Retail/E-Commerce Experience Minimum Of 5 Years Of Consumer Insights Experience Significant experience with different methods of quantitative, qualitative, syndicated and first-party insight tools Experience analyzing syndicated and secondary data sources, as well as macro trend analysis Show more Show less

Designer All Levels Role Summary Designer of all levels, with excellent Revit skills. We believe the best architecture comes from a synthesis of all the elements that separately comprise and inform the character of a building: the structure that holds it up; the services that allow it to function; its ecology; the quality of natural light; the symbolism of the form; the relationship of the building to the skyline or the streetscape; the way you move through or around it; and last but not least, its ability to lift the spirits. Role Definition Job Title: Designer Reporting to: Project Leader of the current project on a day-to-day basis, and ultimately to the Senior Partner Responsibilities Prepare, develop, and edit drawings, models, images, and other documents under the guidance of the project leader Seek to understand the design project Develop representations of design options for discussion with the design team Record evidence of professional experience in accordance with RIBA or equivalent standards (e.g., AIA) Comply thoroughly with Foster + Partners procedures and standards Assist the Partner or Senior Partner as required Champion equity, diversity, and inclusion (EDI) by integrating EDI into relevant workstreams Qualities and Skills Required Demonstrated ability to undertake listed responsibilities Legally permitted to work in the country of employment Strong design understanding supported by a solid portfolio Proficiency in multiple media for design development and documentation Flexible, open to new working methods, and committed to lifelong learning Understanding of design decisions made by others Excellent organisational skills Capable of handling sensitive and confidential information Self-motivated and responsible Proactive and able to demonstrate initiative Strong interpersonal skills and team spirit Flexible and adaptable attitude Ability to build positive relationships at all levels, internally and externally Resilient under pressure, with the ability to prioritise and meet deadlines effectively Works effectively as part of a team, assisting and supporting others

locationsIndia, Bangalore time typeFull time posted onPosted 18 Days Ago job requisition idJR0271803 Job Details: About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.Tech/M.Tech +6 Years of relevant industry experience. Having achieved multiple tape-outs reaching production with first pass silicon. Ability to drive and improve digital design methodology to achieve high quality first silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug. Have experience working in GPU/CPU domain. Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule. Strong verbal and written communication skills. Good understanding of verilog and system verilog, synthesizable RTL. Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Looking for below - Architect/Lead ASIC designer/Lead Design verification/Lead Formal Verification/Lead Emulation/Lead Synthesis Engineer/Lead Implementation Engineer/Lead DFT Engineer/Lead Share your updated CV at jatin@smrd.in

The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assesses architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services. Key Responsibilities Provide technical leadership to define, enable, implement, automate and drive tool/flow/methodology to improve SoC integration efficiency. quality, cost and predictability. Work with architects and design team to understand and continuously improve design process from specification to tapeout. Interface with the architecture, SoC integration, power, Design implementation, Power, Design Verification and Physical design teams to identify complex technical issues/risks and optimize the implementation efficiency and cost. Support the SoC Design and Integration team on project execution. You should be familiar with SoC level Clock and Reset, low power design, UPF, CDC/RDC/LINT, DFT, top level integration of connectivity, system bus, peripherals and processor. We are looking for someone who is technically hands on and a great team player. Preferred Experience Bachelor’s or Master’s degree in related discipline with 15+ years' experience preferred. Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: SoC integration, Frontend-design, Design Verification, Design Emulation, System/performance/power modeling, Design handoffs, Design management, Design reuse, CAD/Automation algorithms. Experience analyzing Design and Verification methodologies/flows to identify bottlenecks, left-shift opportunities, and Demonstrated tools/flows/methodologies/automation expertise in SoC integration, Verification, Emulation, low power design, power optimization, Functional Safety, System modeling, Synthesis and anlysis. Experience with scripting in Perl, Python, TCL, and C/C++. Excellent communication and problem solving skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies. The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $202,900 to $279,000 annually More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. Show more Show less

Company Description SlideXpress is a full-service B2B communications and insights service provider, delivering on-demand knowledge & insights, presentation formatting, and digital design services. Our team works with Fortune 500 companies, consultancies, financial institutions, and high-growth start-ups across various geographies and industries. SlideXpress's offerings mimic McKinsey & Co.'s research and insights services, providing intelligence and actionable information to aid decision-making. Our presentation design services span from basic slide creation to complex animations and interactive infographics, all adhering to best-practice communication and design principles. With a team trained by ex-McKinsey consultants, we ensure that your message is delivered clearly, crisply, and concisely. Role Description This is a full-time on-site role for a Senior Research Associate, based in Mumbai. The Senior Research Associate will be responsible for conducting in-depth research and analysis, synthesizing information to deliver actionable insights, and supporting clients in solving business problems across various industries. The role includes developing detailed reports, creating presentations, managing data sources, and collaborating with teams to ensure high-quality deliverables. Qualifications Strong Research and Analytical skills, including data collection and synthesis Proficiency in creating detailed Reports and Presentations Excellent written and verbal Communication skills Ability to manage multiple Data Sources and Statistical Analysis Experience in client-facing roles and Collaboration with diverse teams Attention to detail and commitment to delivering high-quality work Bachelor's or Master's degree in Business, Economics, or related field Prior experience in consulting or a similar research role is a plus Proficiency in Microsoft Office Suite, especially Excel and PowerPoint Show more Show less

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Lead Software Engineer Location: Noida Experience: 4-6 Years Job Description Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence’s Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product. Job Responsibilities The role’s day to day responsibilities cover: R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills. Job Qualifications Extensive experience developing large, high-quality, object-oriented C++ based applications is required Extensive experience with debugging and tuning of C++ code is required Expertise in data structures and algorithms is required Experience and understanding of EDA timing concepts and time constraints (SDC) is highly desirable Experience developing multi-core applications on Linux is highly desirable Experience developing on Linux with gcc is desirable Hardware knowledge and background in RTL design and/or verification is highly desirable. Position Qualifications B.E. in EE/ECE/CS or Equivalent Good understanding of Digital Electronics. Prior knowledge of Verilog and STA tools required. We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Murf AI , we're simplifying multimedia creation by harnessing the power of artificial intelligence. Our platform empowers users to craft high-quality voiceovers effortlessly, without the need for recording equipment. Some interesting facts about Murf AI: Customers in 100+ countries 8Mn+ registered users 6X growth in revenue in last 12 months 120+ voices in 20+ languages offered by Murf Studio Rated by G2 as Top 10 Fastest Growing Products in 2024 We are working on bleeding-edge research problems, in synthetic speech, synthetic video and dubbing Job Summary : We are seeking a seasoned Python Developer with 1-3 years of experience . In this role, you will work closely with research engineers and linguists to develop and enhance NLP systems in the speech synthesis domain. This position requires strong analytical and critical thinking skills, effective communication, and a passion for creating high-quality software. Roles & Responsibilities: Develop NLP systems according to the project requirements Collaborate with international language experts to incorporate diverse linguistic features Work with large datasets to support language learning and model training Analyse and implement changes as needed, ensuring all bugs are addressed and resolved Deliver high-quality code with zero defects by following industry best practices and maintaining rigorous testing standards Contribute to patent filing and intellectual property protection activities, as applicable Skills & Qualifications: Bachelor's or Master's degree in Computer Science, Engineering, or a related field from Tier 1 Colleges 1-3 years of experience in Python development Experience with NLP and machine learning frameworks such as NLTK, spaCy, TensorFlow, or PyTorch Strong problem-solving skills and ability to implement algorithms efficiently Experience working with large datasets and data preprocessing techniques Ability to write clean, maintainable, and efficient code Familiarity with version control systems (e.g., Git) Excellent communication skills and ability to work effectively in a team environment Attention to detail and commitment to delivering high-quality, bug-free software Extra Awesome Experience with speech synthesis or related domains Knowledge of additional programming languages like Java Knowledge of Web servers and databases Benefits/Perks: Collaborative and stimulating work environment Opportunity to work with cutting-edge technologies and make a significant impact in the field of generative video AI Insurance/healthcare coverage as per company policy Leaves available as per company policy Why Murf.ai? Murf AI is revolutionizing creative workflows for businesses through the utilization of our cutting-edge AI technology. Recognized as a consistent Leader and Momentum Leader on G2 in 2022 and 2023, we empower L&D and creative teams to evolve into dynamic creative powerhouses. With a focus on cutting-edge research and innovation, a positive work culture, and real impact in the AI-driven space, Murf.ai is one of the fastest-growing companies in the AI voice space. Join us at this pivotal moment, where your ideas matter, and your leadership can leave a lasting impact. If you're ready for a challenge and have the vision to lead from the front, Murf.ai is where your journey into the next chapter of AI innovation begins. Show more Show less

Preferred Qualifications: Experience in Memory controller, DDR4/5, LPDDR4/5, HBM memory protocols Experience in GLS is added advantage. Candidate with 10+ yrs exp in Synthesis/STA role Experience in handling complex data path-oriented multi-million gate synthesis Working Knowledge of Physical synthesis using tools like Genus, Design Compiler Experience in debugging for multi-clock domains hierarchical/flat timing analysis. Hands-on experience in LEC along with strong debugging skills for resolving issues/aborts. Netlist and constraint sign in checks and validation. Prime time constraint development at full chip level and clean up. Multimode multi corner timing knowledge and timing closure at block/top level using tools like DMSA Excellent debugging skills in timing convergence issues and ability to come up with creative solutions . Technical leadership and ability to mentor and make the team deliver

Python Software Development Sr.specialist Job Description In these roles, you will be responsible for: Design, implement, and test generative AI models using python and various frameworks such as Pandas, TensorFlow, PyTorch, and OpenAI. Research and explore new techniques and applications of generative AI, such as text, image, audio, and video synthesis, style transfer, data augmentation, and anomaly detection. Collaborate with other developers, researchers, and stakeholders to deliver high-quality and innovative solutions. Document and communicate the results and challenges of generative AI projects. Required Skills for this role include: Technical skills 5 to 7 years’ Experience in developing Python frameworks such DL, ML, Flask At least 2 years of experience in developing generative AI models using python and relevant frameworks. Strong knowledge of machine learning, deep learning, and generative AI concepts and algorithms. Proficient in python and common libraries such as numpy, pandas, matplotlib, and scikit-learn. Familiar with version control, testing, debugging, and deployment tools. Excellent communication and problem-solving skills. Curious and eager to learn new technologies and domains. Desired Skills: Knowledge of Django, Web API Proficient exposure on MVC. Preferences: Graduate degree in Computer Science with 4 years of Python based development. Gen AI Framework Professional Certification Show more Show less

Join Our Aprisa Team! Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. We Make Real What Matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5-8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and Tcl. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069944 Show more Show less

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience OR Master's degree in the above fields and 2+ years of relevant experience OR PhD in the above fields and 1+ year of relevant experience Bachelor's degree in Science, Engineering or a closely related field Experience with digital design and RTL development Experience with front-end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, and Synopsys PrimeTime Preferred Qualifications: Knowledge and experience in graphics design and development Proficient in scripting languages such as Perl, TCL, and shell scripting Strong interpersonal and team collaboration skills with the ability to work independently Ability to problem solve complex and unique design issues Familiarity with latest EDA tools for synthesis, formal verification, timing analysis, and physical design

General Summary: As a SoC Power & Architecture Engineer, you will collaborate with cross-functional teams to develop and optimize power architecture for mobile SoC ASICs. Your expertise will drive low-power design techniques and power management strategies that enhance chip efficiency and performance. Skills and Experience: Required (412 years): Low power intent concepts and languages (UPF or CPF) Power estimation and reduction tools (PowerArtist, PTPX, Calypto) Power dissipation and savings techniques, including dynamic clock and voltage scaling Power analysis (leakage and dynamic) and thermal impact evaluation Power software features for optimization Voltage regulators (Buck converters, Low Dropout regulators) ASIC power grids and PCB power distribution networks Preferred / Additional Skills: Mobile baseband application processor chipset and power grid knowledge UPF-based synthesis and implementation with Design Compiler Structural low power verification tools (CLP, MVRC) Excellent written and verbal communication skills Responsibilities: Define chip and macro-level power domains Conduct system-level power modeling and mixed-signal power analysis Design power islands, power gating, and power isolation techniques Develop structural low-power design elements such as level shifters and isolation cell topologies with associated design rules Perform architectural analysis and develop digital power optimization logic, circuits, and software Collaborate with Power Management IC developers for power grid planning Create detailed architecture and implementation documentation Education and Minimum Qualifications: Required: Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 3+ years of hardware engineering experience OR Master's degree with 2+ years of hardware engineering experience OR PhD with 1+ year of hardware engineering experience Preferred: Master's degree in Computer Engineering or Electrical Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.

Join Our Aprisa Team! Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. We Make Real What Matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5- 8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

Job Summary:-_ Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for IP / SS domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation. Key Responsibilities: Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team. Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation. Architect and Design complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc. Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules. Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that. Key Skills Self starter with 10-14 years of hands-on experience to Architect and Design complex IP design / Sub-system with minimal supervision. Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing. Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2. Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces. Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI. Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling. Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage. Have worked on Testbench and Testplan development closely with the verification team. Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage. Key Soft Skills Proficient skills in both written and verbal communication. Can articulate well. Has a sense of Ownership and engages everyone with Trust and Respect. Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements: 2+ years of experience with a Bachelor’s/ Master’s degree in Electrical engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail myhr.support@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3063951 Show more Show less

PERSONAL CHARACTERISTICS & BEHAVIOURS Ability to work with external suppliers & CFT. Good synthesis capacity (be simple) Supplier management Capacity to analyse and solve issues. Strong communication skills, Negotiation skills, Ability to work with deadlines & without supervision, Analytical skills and logical thinking, Adaptability and learning skills. Able to plan schedule from RFQ to SOP covering all intermediate factors. Basic knowledge about Validations (Engine/Gearbox) Ability to work with deadlines & without supervision Capable of training the Engineer’s(Beginner’s) Can deal with critical problems & malfunctions Show more Show less

Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in all stages of the design and development cycles Synthesis, Static Timing Analysis and LEC of SoC/Cores Full chip and block level timing closure, IO budgeting for blocks Logical equivalence check between RTL to Netlist and Netlist to Netlist Knowledge of low-power techniques including clock gating, power gating and MV designs ECO timing flow Proficient in scripting languages (TCL and Perl). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Bachelors / Masters degree in electrical or electronics engineering with 3-6 yrs of experience is preferred