2263 Synthesis Jobs - Page 36

EEAS Headquarters job No 461169 WE ARE The European External Action Service (EEAS) supports the High Representative in the exercise of her mandate to conduct and implement an effective and coherent Union’s Common Foreign and Security Policy (CFSP), to represent the EU and to chair the Foreign Affairs Council. It also supports the High Representative in her capacity as Vice-President of the Commission with regard to her responsibilities within the Commission in the external relations field, including the coordination of other aspects of the EU's external action. The EEAS works in close cooperation with the EU Member States, the General Secretariat of the Council, the services of the Commission and the Secretariat General of the European Parliament. The recruiting Division RM.SCS.2 - Public Procurement, Contracts and Finance is to be responsible for procurement and contracts for Headquarters and Delegations and for ex ante financial verification of transactions stemming from public contracts. It supports and advises the authorising officers by sub- delegation in the management of their public contracts including their risk management. Contracts covered by the Division are those subject to the Public Procurement Directive (services, supplies and works) and exclude all kind of employment contracts or building contracts. The Public Procurement Sector establish the public procurement policies, processes and procedures for services, supplies and works contracts in the EEAS as well as provide support to the users. It also provide tools and methodologies to support professional procurement practice, i.e. ensure the availability of tools and processes to deliver smart procurement, such as eProcurement tools, guidelines and templates with corresponding training, support and expertise, aggregation of knowledge and exchange of good practice. Moreover, acting on behalf of the responsible Authorising Officer by sub-delegation (AOSD), centrally manage the public procurement procedures leading to services, supplies and works contracts awarded by the EEAS whose estimated value is above the 2014/24/EU Directive thresholds for services and supplies, and above EUR 500.000 for works (later referred to as "high-value procedures"). WE PROPOSE The position of Procurement Assistant, contract agent FG.III as per article 3b of the Conditions of Employment of Other Servants of the European Union (hereafter, the “CEOS”)[1]. PLACE and DATE OF EMPLOYMENT ‎EEAS Headquarters, Brussels, Belgium Post available: 01 September 2025 LEGAL BASIS The vacancy is to be filled in accordance with the conditions stipulated under the CEOS, in particular Article 82 thereof. In case of recruitment, the successful candidate will be offered a contract agent position (Function group III), on the basis of a contract with an initial duration of one year that may be successively renewed up to a maximum duration of six years[2], subject to the maximum duration of engagement by the EEAS allowed under successive limited duration contracts of different types[3]. WE LOOK FOR Responsibilities A dynamic, proactive and highly motivated contract agent responsible for legal analysis/advice on procurement. S/he will be part of a team reporting to the Head of the Public Procurement Sector. S/he will have as main responsibilities: Analyse the operational needs, translate them into procurement documents, prepare and run of high-value procurement procedures with HQ Divisions and EU Delegations; Act as the focal point for a number of horizontal tasks such as the preparation/update of templates, standard documents and guides relating to procurement, including for (very)low and middle-value contracts, green procurement or any other manual on procedures; Provide support in particular in relation to the use of the tools developed for procurement procedures and contracts; Provide legal analysis, advice and assistance on procurement matters to HQ Divisions and EU Delegations worldwide; Prepare synthesis notes and briefings to facilitate decision-making by the hierarchy; Participate to the preparation/update of the Annual Procurement Plan of the EEAS; Train EEAS staff on procurement topics and hold information sessions on the Financial Regulation, procurement guidelines and templates; Be proactively involved in the broader activities of the Division, actively cooperating with other Sectors of the Division (Contracts’ management and Finance). Eligibility criteria [4] Further to the conditions set out in Article 82 of the CEOS, candidates must: have passed a valid EPSO CAST in a valid function group for this post, or be registered in the EPSO Permanent CAST in a valid function group for this post (https://epso.europa.eu/en/job-opportunities/open-for-application). In the latter case, while the registration will make the candidate eligible for the selection procedure, the recruitment of a candidate on this vacant post will be subject to his/her successfully passing the CAST exam; have a level of post-secondary education attested by a diploma or a level of secondary education attested by a diploma giving access to post-secondary education and appropriate professional experience of three year; have the capacity to work in the languages of the CFSP and external relations (English and French) necessary for the performance of their duties; be a national of one of the Member States of the European Union and enjoy full rights as a citizen. Selection criteria Candidates Should have minimum two (2) years of professional experience providing legal analysis/advice on procurement matters; have strong drafting and analytical skills combined with sound legal judgement; have sound knowledge of the EU Financial Regulation; have the ability to communicate complex issues simply and to identify practical solutions; have excellent drafting and communication skills both in English and French (C1 and above); be service-oriented and have strong prioritising skills; be a flexible team player, willing to integrate a small team and to ensure business continuity; have the ability to maintain diplomatic relations and to ensure representation and communication in a complex, multicultural environment; have excellent communication skills and the ability to establish and maintain a network of contacts both within and outside the EEAS. Furthermore experience of working in a team in multi-disciplinary and multi-cultural environment; experience in working with or within other EU institutions, especially in the area of procurement and legal analysis/advice; written proficiency in Spanish will be considered as strong assets. CONDITIONS OF RECRUITMENT AND EMPLOYMENT CONFLICT OF INTEREST AND SECURITY RISKS As a matter of policy, applications by individuals who have dual nationality of which one of a non-EU country, will be considered on a case-by-case basis taking account in particular of the functions attributed to the vacant post. The EEAS also examines if there could be a conflict of interest or security risks. In this context, candidates shall fill in with their application a declaration of potential conflict of interest (see attached) MEDICAL CLEARANCE The signature of the contract will be subject to prior favourable opinion of the Medical Service. PERSONNEL SECURITY CLEARANCE (PSC) This post is currently not identified as a post which requires Personnel Security Clearance (hereafter, the “PSC”) to access EU classified information (EUCI) in accordance with point 7 of Annex A I of the Decision ADMIN(2023) 18 on the security rules of the EEAS[5] and as implemented by Decision ADMIN(2019) 7 on Security Clearance Requirements and Procedures for the EEAS of 08 March 2019 and its implementing decisions. Nonetheless, candidates are informed that the list of posts requiring a PSC in the EEAS Headquarters is subject to regular review and that the current post might be identified in the future as a post which requires PSC. If required after the taking of duty, the selected candidate will need to be in a position to obtain a valid PSC issued by the competent authority of their Member State in accordance with national laws and regulations. In case of failure to obtain or renew the required PSC, the AACC may take the appropriate measures in accordance with Article 3(3) of the Decision ADMIN(2019) 7 on Security Clearance Requirements and Procedures for the EEAS of 08 March 2019. Description of the EU classified information levels is available under Article 2 of Annex A of the Decision ADMIN(2023) 18 on the security rules of the EEAS. EQUAL OPPORTUNITIES The EEAS is committed to an equal opportunities policy for all its employees and applicants for employment. As an employer, the EEAS is committed to promoting gender equality and to preventing discrimination on any grounds. It actively welcomes applications from all qualified candidates from diverse backgrounds and from the broadest possible geographical basis amongst the EU Member States. We aim at a service, which is truly representative of society, where each staff member feels respected, is able to give their best and can develop their full potential. Candidates with disabilities are invited to contact CONTRACTAGENTS-HQ@eeas.europa.eu in order to accommodate any special needs and provide assistance to ensure the possibility to pass the selection procedure in equality of opportunities with other candidates. If a candidate with a disability is selected for a vacant post, the EEAS is committed to providing reasonable accommodation in accordance with Art 1(d)(4) of the Staff Regulations. APPLICATION AND SELECTION PROCEDURE [6] Please Send Your CV And Cover Letter (with Your EPSO CAST Number), In English Or French, And The Attached Declaration Of Potential Conflict Of Interest Via Email, With Reference To The Vacancy Number In The Subject Field, To RM-SCS-2@eeas.europa.eu Deadline for sending application: 25/07/2025 at 12.00 noon (CET) . Candidates shall draft their CV using the Europass CV, which can be found at the following internet address: http://europass.cedefop.europa.eu/en/documents/curriculum-vitae. Late applications will not be accepted . The selection panel will make a pre-selection on the basis of the qualifications and professional experience described in the CV and motivational letter, and will produce a shortlist of eligible candidates who best meet the selection criteria for the post. Please note that only shortlisted candidates will be informed about the outcome of the pre-selection phase. The candidates who have been preselected will be invited for an interview by a selection panel. The selection panel may decide, subsequent to the interview, to organise written tests, either for all pre-selected candidates or to the best ranked ones. The content of such written tests will be defined by the selection panel and may include, but not be limited to, multiple choice questions, open questions and/or topics for a short essay. Pre-selected candidates without a valid CAST shall be invited to sit the CAST exam before or after the interview stage (in accordance with the eligibility criteria set out above). The panel will then recommend a shortlist of candidates for a final decision by the Authority Authorised to Conclude Contracts of Employment (hereafter, the “AACC”). The AACC may decide to interview the candidates on the final shortlist before taking this decision. It is recalled that the selection procedure may be terminated at any stage in the interest of the service. In the interest of the service, after identifying the candidate that best fits the requirements of the post as set out in the vacancy notice, the AACC may also establish a reserve list of candidates. These candidates shall be informed that the reserve list shall remain valid for a period of one year from when it is established and that it may be used to fill the same post or an equivalent post in the EEAS with the same job profile. [1] Staff Regulations of Officials of the European Union (SR) and the Conditions of Employment of Other Servants of the European Union (CEOS). [2] Article 8 of the Commission Decision C(2017) 6760 of 16.10.2017 on the general provisions for implementing Article 79(2) of the Conditions of Employment of Other Servants of the European Union, governing the conditions of employment of contract staff employed by the Commission under the terms of Articles 3a and 3b thereof. [3] Decision ADMIN(2023) 24 on the maximum duration of engagement by the European External Action Service of non-permanent staff under successive limited duration contracts of different types, and on the minimum lapse of time between successive contracts under Article 2(e) of the CEOS. [4] All the eligibility criteria must be met on the closing date for applications to this post. [5] OJ C 263, 26 July 2023, p.16. [6] Your personal data will be processed in accordance with Regulation (EU) 2018/1725, as implemented by ADMIN(2019)8 Decision of the High Representative of the Union for Foreign Affairs and Security Policy. The privacy statement is available on the Europa website: (https://www.eeas.europa.eu/eeas/eeas-privacy-statement-data-protection-notice-purpose-processing-personal-data-related-public_en) and on the EEAS Intranet:(https://intranet.eeas.europa.eu/page/eeas-work/data-protection/privacy-statements-dp-notices).

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Machine Learning Engineering General Summary: Job Overview: Qualcomm is a company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. We are investing in several supporting technologies including 4G, 5G, Edge Computing, and Deep Learning. The Qualcomm AI team is developing hardware and software for Machine Learning solutions spanning the data center, edge, infrastructure, automotive markets and beyond. We are seeking ambitious, bright and innovative engineers with experience in Machine learning frameworks, compiler technology, vectorization and optimization, and machine learning toolchains. Job activities span the whole product life cycle from early design to commercial deployment. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must. We are looking to staff engineers at multiple levels in systems & software, integration and test. Details of one of the roles we are looking to staff are listed below. Responsibilities: Research, design, develop, enhance, and implement the different components of machine learning framework, compilers based on performance and code-size needs of the customer workloads and benchmarks. Analyze software requirements, determine the feasibility of design within the given constraints, consult with architecture and HW engineers, and implement software solutions best suited for Qualcomm's SOCs. Analyze and identify system level integration issues, interface with the software development, integration and test teams. Minimum Qualifications Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering or related work experience. Preferred Qualifications Has internal working knowledge of Machine learning frameworks like Pytorch, Tensorflow. Has experience in model level optimization using techniques like torch compile. LLVM or any industrial strength compiler development experience is a plus. Knowledge of the structure and function of the compiler internals. Hands on experience writing SIMD and/or multi-threaded high-performance code is a plus. Hands-on experience implementing DSP Kernels a plus Hands-on Experience in C/C++, Python development (5+ years) Hands-on Experience with Object Orientated Design, TDD development solutions such as GoogleTest etc. (4+ years) Experience with Source Code and Configuration management tools, git knowledge is required Willingness to work in a cohesive software development environment with ability to work on low level implementation (code & test) and interfacing with hardware and simulators Experience in neural network architectures + ML compiler workload synthesis, a plus Prior working experience of hardware accelerators and hardware software co-design Experience in using C++ 14/17 (advanced features) Experience at both the firmware (RTOS) and system level (Linux) in SOC Experience of profiling software and optimization techniques Passion to drive to develop leading-edge "deep learning" framework and algorithms working on mobile and embedded platforms. Minimum Qualifications: Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Science, Engineering, Information Systems, or related field and 3+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. OR PhD in Computer Science, Engineering, Information Systems, or related field and 2+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3076831

Job Description About the Role Extreme Event Solutions at Verisk (previously AIR Worldwide) is the scientific leader and most respected provider of risk modeling software and consulting services. Extreme Event Solutions at Verisk founded the catastrophe modeling industry in 1987 and today models the risk from natural catastrophes, terrorism, and pandemic outbreaks in 90 countries. Verisk offers the opportunity to work with advanced technologies, global clients, and hundreds of the most innovative, talented minds in the industry. Become a member of our Atmospheric Perils Vulnerability team and join our growing Research and Modeling department in our Hyderabad, India office. Use your knowledge of civil engineering and statistics to develop models of extreme catastrophic events (i.e., hurricanes, tornadoes, storm surge, flood etc.) and assess building performance in the context of such events. This Research Engineer position is responsible for developing, enhancing and supporting the engineering/vulnerability components of Verisk’s atmospheric perils based portfolio risk analysis models that cover worldwide regions, including perils such as straight-line wind from tropical cyclones, severe convective storms and winter storms, hail, snow, and freezing temperatures. General responsibilities include identifying the impact that these perils can have on the built environment, including physical damage which can result in monetary loss to buildings/infrastructure, contents, and loss of use (downtime). The candidate will work closely with a team of structural engineers, meteorologists, hydrologists, hydraulic engineers, statisticians, and specialists in financial application of probabilistic risk assessment. The candidate is expected to be highly motivated, detail oriented, well organized, and an independent worker and collective team player who can present and explain results to internal stakeholders and external clients. The evolving nature of research work at Verisk creates unique and challenging problems that spark innovation and growth and creates opportunities for its employees. A successful candidate should have a desire to use problem-solving skills in applying sound engineering principles to solve unique and challenging problems in the fields of civil/structural engineering and risk assessment. It is expected that candidates will be highly motivated, detail-oriented, well-organized, able to perform high-quality self-directed research, have outstanding written and verbal communication skills, and be team-oriented. Responsibilities About the Day-to-Day Responsibilities of the Role As a member of our Atmospheric Perils Vulnerability Team, your day-to-day responsibilities will include the following: Data acquisition, synthesis, and analysis for the purpose of understanding building inventory, and its vulnerability in lieu of industry insured losses and insurance claims data subjected to atmospheric-based hazards in multiple regions worldwide Willingness to learn and work with a variety of proprietary Verisk datasets and find ways to integrate the same into Verisk’s extreme event models Analytical analyses and research aimed towards the development of vulnerability functions and monetary loss curves for structural and non-structural building and infrastructure components subjected to hazards such as wind, tornadoes, hail, and snow for several regions of interest worldwide Implementation of research into Verisk’s portfolio risk analysis models, including programming loss simulation codes and analysis tools, and probabilistic risk assessment validation Use of GIS and similar tools for data visualization and analysis Real-time and virtual building damage assessments due to natural catastrophes during and after significant events Preparation and presentation of work at staff internal and client external meetings as well as technical writing for internal and external publications and client-facing documentation Qualifications About You and How You Can Excel in This Role Ph.D. in Civil Engineering with a special emphasis in Structural Engineering Experience in performance-based design, probabilistic and stochastic risk assessment and modeling, and reliability theory with applications to the field of structural engineering Proficiency in C/C++, Python along with other productivity software including R, MATLAB, Microsoft Office Excellent written and verbal communication skills Strong organizational and excellent documentation skills Knowledge of GIS applications (e.g. ArcView) and SQL server is a plus About Us For over 50 years, Verisk has been the leading data analytics and technology partner to the global insurance industry by delivering value to our clients through expertise and scale. We empower communities and businesses to make better decisions on risk, faster. At Verisk, you'll have the chance to use your voice and build a rewarding career that's as unique as you are, with work flexibility and the support, coaching, and training you need to succeed. For the eighth consecutive year, Verisk is proudly recognized as a Great Place to Work® for outstanding workplace culture in the US, fourth consecutive year in the UK, Spain, and India, and second consecutive year in Poland. We value learning, caring and results and make inclusivity and diversity a top priority. In addition to our Great Place to Work® Certification, we’ve been recognized by The Wall Street Journal as one of the Best-Managed Companies and by Forbes as a World’s Best Employer and Best Employer for Women, testaments to the value we place on workplace culture. We’re 7,000 people strong. We relentlessly and ethically pursue innovation. And we are looking for people like you to help us translate big data into big ideas. Join us and create an exceptional experience for yourself and a better tomorrow for future generations. Verisk Businesses Underwriting Solutions — provides underwriting and rating solutions for auto and property, general liability, and excess and surplus to assess and price risk with speed and precision Claims Solutions — supports end-to-end claims handling with analytic and automation tools that streamline workflow, improve claims management, and support better customer experiences Property Estimating Solutions — offers property estimation software and tools for professionals in estimating all phases of building and repair to make day-to-day workflows the most efficient Extreme Event Solutions — provides risk modeling solutions to help individuals, businesses, and society become more resilient to extreme events. Specialty Business Solutions — provides an integrated suite of software for full end-to-end management of insurance and reinsurance business, helping companies manage their businesses through efficiency, flexibility, and data governance Marketing Solutions — delivers data and insights to improve the reach, timing, relevance, and compliance of every consumer engagement Life Insurance Solutions – offers end-to-end, data insight-driven core capabilities for carriers, distribution, and direct customers across the entire policy lifecycle of life and annuities for both individual and group. Verisk Maplecroft — provides intelligence on sustainability, resilience, and ESG, helping people, business, and societies become stronger Verisk Analytics is an equal opportunity employer. All members of the Verisk Analytics family of companies are equal opportunity employers. We consider all qualified applicants for employment without regard to race, religion, color, national origin, citizenship, sex, gender identity and/or expression, sexual orientation, veteran's status, age or disability. Verisk’s minimum hiring age is 18 except in countries with a higher age limit subject to applicable law. https://www.verisk.com/company/careers/ Unsolicited resumes sent to Verisk, including unsolicited resumes sent to a Verisk business mailing address, fax machine or email address, or directly to Verisk employees, will be considered Verisk property. Verisk will NOT pay a fee for any placement resulting from the receipt of an unsolicited resume. Verisk Employee Privacy Notice

Job Description Some careers have more impact than others. If you’re looking for a career where you can make a real impression, join HSBC and discover how valued you’ll be. HSBC is one of the largest banking and financial services organizations in the world, with operations in 62 countries and territories. We aim to be where the growth is, enabling businesses to thrive and economies to prosper, and, ultimately, helping people to fulfil their hopes and realize their ambitions. We are currently seeking an experienced professional to join our team in the role of Company Secretarial Assistant Principal Responsibilities Contributing to the development and implementation of corporate governance best practice, corporate governance frameworks and best practices in accordance with Group and relevant industry standards. Reliable and timely arrangements made for board and committee meetings, including booking meeting rooms and facilities, preparing agendas, preparing skeleton minutes, tracking actions, drafting the annual planner, circulating papers in a timely manner and, where appropriate, (and in all cases using the templates and platforms promoted by CG&S). Collate, draft and/or review the papers to the board of directors and committees and communicate appropriate recommendations for action. Following appropriate processes and procedures and understanding statutory and regulatory obligations and support the CG&S onshore team in fulfilling the required obligations. Manage governance framework to support all relevant entity management activities as per the local laws and regulations governing the entities. Maintenance of accurate and complete statutory records on the Group Internal Corporate Database and timely filing of statutory returns with relevant regulatory/government authorities/ bodies. Accurate and timely cosec input to annual reporting documents including statutory accounts of HSBC Group companies also supporting the process for the annual review of board/committee terms of reference, effectiveness and other policies of the Group, including the SAF. Collaborate with cross functional teams across onshore and offshore stakeholders to ensure due discharge of all required compliance obligations. Suggesting improved processes to increase efficiency of processes, control costs and avoid operational losses within the Department. To assist with the on-boarding, induction and conflict of interest reviews of directors and other relevant individuals to HSBC and contribute to the development of strategic and operational objectives of CG&S function. Requirements Company Secretarial qualification with minimum relevant of 6 years experience. Strong understanding and experience of maintaining entity records and statutory registers (electronic registers experience valuable but not essential) Experience in international governance/compliance preferred. Understanding of the theory and tools of governance. Outstanding written/verbal communication and presentation skills. Be change oriented and able to cope with pressure and tight deadlines. Strong analytical capability with the ability to synthesis complex data. Able to understand and consolidate diverse and complex business information and identify / mitigate risk issues. Ability to look at the bigger picture, produce high quality work, as well as have a keen eye for detail. Accountability, responsibility and willingness to go beyond core responsibilities in times of necessity. You’ll achieve more at HSBC HSBC is an equal opportunity employer committed to building a culture where all employees are valued, respected and opinions count. We take pride in providing a workplace that fosters continuous professional development, flexible working and, opportunities to grow within an inclusive and diverse environment. We encourage applications from all suitably qualified persons irrespective of, but not limited to, their gender or genetic information, sexual orientation, ethnicity, religion, social status, medical care leave requirements, political affiliation, people with disabilities, color, national origin, veteran status, etc., We consider all applications based on merit and suitability to the role.” Personal data held by the Bank relating to employment applications will be used in accordance with our Privacy Statement, which is available on our website. Issued By HSBC Electronic Data Processing (India) Private LTD***

Job Description Some careers have more impact than others. If you’re looking for a career where you can make a real impression, join HSBC and discover how valued you’ll be. HSBC is one of the largest banking and financial services organizations in the world, with operations in 62 countries and territories. We aim to be where the growth is, enabling businesses to thrive and economies to prosper, and, ultimately, helping people to fulfil their hopes and realise their ambitions. We are currently seeking an experienced professional to join our team in the role of Company Secretarial Assistant. Principal Responsibilities Contributing to the development and implementation of corporate governance best practice, corporate governance frameworks and best practices in accordance with Group and relevant industry standards. Reliable and timely arrangements made for board and committee meetings, including booking meeting rooms and facilities, preparing agendas, preparing skeleton minutes, tracking actions, drafting the annual planner, circulating papers in a timely manner (and in all cases using the templates and platforms promoted by Corporate governance and secretariat. Collate, draft and/or review the papers to the board of directors and committees and communicate appropriate recommendations for action. Following appropriate processes and procedures and understanding statutory and regulatory obligations and support the CG&S onshore team in fulfilling the required obligations. Manage governance framework to support all relevant entity management activities as per the local laws and regulations governing the entities. Maintenance of accurate and complete statutory records on the Group Internal Corporate Database and timely filing of statutory returns with relevant regulatory/government authorities/ bodies. Collaborate with cross functional teams across onshore and offshore stakeholders to ensure due discharge of all required compliance obligations. Assist with the on-boarding, induction and conflict of interest reviews of directors and other relevant individuals to HSBC. To respond to requests for CG&S owned information and assist in CG&S centralized ad hoc projects. To contribute to the development of strategic and operational objectives of CG&S function. Proven ability of innovativeness and challenging the status quo to ensure processes and ways of working remain fit for purpose in a dynamic and ever-changing business and regulatory environment. Requirements Company Secretarial qualification with relevant of 4 years experience Strong understanding and experience of maintaining entity records and statutory registers (electronic registers experience valuable but not essential) Experience in international governance/compliance preferred. Understanding of the theory and tools of governance. Outstanding written/verbal communication and presentation skills. Be change oriented and able to cope with pressure and tight deadlines. Strong analytical capability with the ability to synthesis complex data. Able to understand and consolidate diverse and complex business information and identify / mitigate risk issues. Ability to look at the bigger picture, produce high quality work, as well as have a keen eye for detail. Accountability, responsibility and willingness to go beyond core responsibilities in times of necessity. You’ll achieve more at HSBC HSBC is an equal opportunity employer committed to building a culture where all employees are valued, respected and opinions count. We take pride in providing a workplace that fosters continuous professional development, flexible working and, opportunities to grow within an inclusive and diverse environment. We encourage applications from all suitably qualified persons irrespective of, but not limited to, their gender or genetic information, sexual orientation, ethnicity, religion, social status, medical care leave requirements, political affiliation, people with disabilities, color, national origin, veteran status, etc., We consider all applications based on merit and suitability to the role.” Personal data held by the Bank relating to employment applications will be used in accordance with our Privacy Statement, which is available on our website. Issued By HSBC Electronic Data Processing (India) Private LTD***

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Chennai Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Turn your weekends into an earning opportunity!

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Bangalore Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Turn your weekends into an earning opportunity!

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Position Title: Trainer/Training Manager, India Job Type: Full-Time, Permanent Location – Mumbai Or Delhi Work Experience – 5+ Year About the company: BCPL – BEAUTY CONCEPTS, established in the year 1996 is a member of the Bahety Group of Companies, one of the most trusted business houses from Kolkata. With a brand porƞolio exceeding 45 leading international brands in fragrances, beauty & cosmetics, BCPL is the preferred partner for international brands in the growing market. With over 30 years of customer understanding across the segments of Mass, Mass Premium, Fashion, Prestige & Luxury, BCPL provides its partners with a competitive edge in a challenging & emerging market like India. Website - https://bcplindia.com/about Job Purpose: To completely deliver the brand's unique identification including Brand History, Product, Knowledge, Brand Core Value, philosophy, soft skills and new launches for the field and office team. To build a strong field (sales & training) team and work with the sales team for sales growth and service improvement. As a Brand Trainer, He/She will play a vital role in ensuring the impeccable execution of APAC education programs and strategic development of training programs. He/She will support the market in elevating the retail team’s standards in key areas of the brand to deliver unsurpassed client services and maintain high image standards through Training & Retail Excellence strategies and support. He/She will also engage and advance the capabilities of the Training and Retail community in the region by driving a robust self-directed learning culture and growth mindset. Key Responsibilities: • Be the key expert person in fragrance education materials, purposes, learning objectives, deliveries, and measurements, including planning, and executing all training sessions to the Field Retail Team. • Collaborate very closely with the dedicated brand manager of BCPL in India for procuring training materials, Cas uniforms and accessories, training frequency of top and reference doors and elevating the overall quality and performance of Client Advisors. • Be responsible for monitoring, tracking, and gather 360 feedback on all market training programs (new and existing). • Support yearly and long-term strategic plans through calibration and synthesis of Bulgari Regional priorities and markets’ needs. • Work closely with the APAC education team and market on a yearly plan to understand and deliver all training programs and initiatives to enhance brand knowledge, retail excellence, and fragrance expertise to the retail team. • Responsible for planning training calendars and budgets to meet the overall business, sales, and marketing objectives. • Be a team player and collaborate with the APAC training team, including leveraging on Best Practices, or highlighting new initiatives in India. • Collaborate with relevant stakeholders to develop, curate, design, implement, and follow up learning and development programs with end-to-end execution (objectives, post-training follow-up and observation, program evaluation, KPIs, etc.). • Reinforce social learning by animating Communities of Practices and key moments in the year for the Training community. • Participate and support onboarding programs as required. • Engage and update the community with inspiring fragrance trends and practices in the learning space. • Lead and coach the Retail team in applying the Retail Excellence approach. • Monitor effective execution of training programs. • Ensure all training program aligns with training strategies/direction and sell-out priorities • Provide proactive support, coaching, follow up and feedback to Field Team. • Identify Training/Coaching Objective and Action Plan for store visit according to the Retail & Training Strategy • Create, review, and enhance content of training program/modules. • Deliver the training program independently, such as SOP training, new CA training, new product training, Selling & Service, relevant skills to their job. • Provide on-site coaching to CA and help them to build confidence while working in the field. • Work with sales team on CA evaluation and development. • Maintain and upgrade CA image. Ensure APAC Grooming Guidelines are followed. • Good at data analysis and management to follow up and ensure the effective training implementation. Person Specifications: The ideal candidate should possess a strong business sense and vision of how Training & Retail Excellence plays a pivotal role in supporting business ambitions, by developing and elevating our greatest asset – People. Strategic in leveraging pedagogic principles to unlock the retail learners’ learning effectiveness and translating them into performance, the candidate seeks to maximize the learner’s potential and capabilities. A passion for continuous learning – fragrance trends, ways of learning, culture, etc. will be essential. This position will require close collaboration with the APAC Training & Retail Excellence function. More than 5 years of experience in training and development is compulsory. Strong interpersonal and written and spoken communication skills in English and Hindi. Ability to develop and deliver client-centric and interactive training to engage the target audience. Strong in coaching & developing skills and able to empower the team. Job Description: Academic / Professional Qualifications  Team leader with a strong focus in the achievement of results  Proven experience of team/department management  Possess dynamism and confidence and at the same time articulate and positive  Genuine interest and appreciation for the fragrance and luxury industry  Excellent presentation skill  Coaching skill is must  Passionate, creative and drive for result  Microsoft Office

Job Title: Physical Design Engineer Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities End-to-end ownership of chip-level and block-level floor planning. Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis, DRC/LVS closure, and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required Strong experience in chip-level and block-level physical design. Hands-on expertise with Innovus and/or Fusion Compiler. Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Skills: block-level physical design,cadence innovus,semiconductor,vlsi design,problem-solving,synopsys fusion compiler,fusion compiler,power management,timing analysis,drc/lvs closure,physical verification,signal integrity,innovus,chip-level physical design,debugging,chip design,physical design

Amex GBT is a place where colleagues find inspiration in travel as a force for good and – through their work – can make an impact on our industry. We’re here to help our colleagues achieve success and offer an inclusive and collaborative culture where your voice is valued. Create your journey at Amex GBT! As a Neo Software Engineer, you’ll join our highly skilled R&D Neo team ! Neo is an online booking tool (OBT) as well as an expense tool for business travel through a SaaS deployment. It allows a user to search and book a business trip in a user friendly and high-performance web application. It gives him access to different transport modes and travel suppliers within the travel policy set by his company. It then gives them the opportunity to claim additional expenses for reimbursement. The service allows to capture VAT, compute policies and reimbursement rules, and much more. Our scrum teams are empowered to develop a leading product with some strong focus on usability, performance, and scalability in an international environment. We’re most proud of our warm and inclusive culture, innovation in the travel & expense tech space, internal promotions, and career advancement opportunities. We’re excited for you to experience our values (People, Passion, and Progress) in action, and look forward to your application. What You’ll Do on a Typical Day Work in a SCRUM team Design, develop and test new applications and features Participate in the evolution and maintenance of existing systems Contribute in the deployment of features Monitor the platform Propose new ideas to enhance the product either functionally or technically What We’re Looking For 8-10yrs of Operational knowledge of C# or python development, as well as in Docker Experience with PostgreSQL or Oracle Knowledge of AWS S3, and optionally AWS Kinesis and AWS Redshift Real desire to master new technologies Unit test & TDD methodology are assets Team spirit, analytical and synthesis skills Passion, Software Craftsmanship, culture of excellence, Clean Code Fluency in English (multicultural and international team) What Technical Skills You’ll Develop C# .NET and/or Python Oracle, PostgreSQL AWS ELK (Elasticsearch, Logstash, Kibana) GIT, GitHub, TeamCity, Docker, Ansible #GBTJobs Location Gurgaon, India The #TeamGBT Experience Work and life: Find your happy medium at Amex GBT. Flexible benefits are tailored to each country and start the day you do. These include health and welfare insurance plans, retirement programs, parental leave, adoption assistance, and wellbeing resources to support you and your immediate family. Travel perks: get a choice of deals each week from major travel providers on everything from flights to hotels to cruises and car rentals. Develop the skills you want when the time is right for you, with access to over 20,000 courses on our learning platform, leadership courses, and new job openings available to internal candidates first. We strive to champion Inclusion in every aspect of our business at Amex GBT. You can connect with colleagues through our global INclusion Groups, centered around common identities or initiatives, to discuss challenges, obstacles, achievements, and drive company awareness and action. And much more! All applicants will receive equal consideration for employment without regard to age, sex, gender (and characteristics related to sex and gender), pregnancy (and related medical conditions), race, color, citizenship, religion, disability, or any other class or characteristic protected by law. Click Here for Additional Disclosures in Accordance with the LA County Fair Chance Ordinance. Furthermore, we are committed to providing reasonable accommodation to qualified individuals with disabilities. Please let your recruiter know if you need an accommodation at any point during the hiring process. For details regarding how we protect your data, please consult the Amex GBT Recruitment Privacy Statement. What if I don’t meet every requirement? If you’re passionate about our mission and believe you’d be a phenomenal addition to our team, don’t worry about “checking every box;" please apply anyway. You may be exactly the person we’re looking for!

1. : Responsible for all kinds of lab activities such as synthesis, purification process, analysis, product testing with in-hand expertise for any product related to R&D as he is well experienced now after two and half year. 2. : He was mostly associated with new product development as high waxy crude Oil PPDs,FIOD MT-04, WCP 1506, WCP 1515, WCP 1505M and Lubricity improver EC5725A on the lab-scale. 3. : Currently, he is involved in the analysis of some market standard downstream products, formulation related activities based on the PPD and sample packing and forwarding activities. 4. : In terms of technology, he has no such experience on the commercialization of products. Only he has done some lab reactions carried out on the modification of PDL 96 / PDM 2014 and EC5725A. Additionally, he was involved in pilot scale trials on the WCP series ongoing project. 5. . It is not a competitor organisation with our Oilf-ield products. He is going to the food industry related to formulation / speciality development. Must be Post Graduate in M.Sc in Polymer.

Mandate Technical Skills: 1. Design, develop, and implement FPGA-based solutions using Max10 and Cyclone 10 platforms. 2. Write and optimize code in Verilog for FPGA programming. 3. Utilize Quartus Prime for FPGA design, synthesis, and implementation. 4. Implement algorithms on FPGA for various applications. 5. Interface FPGA with peripherals and external devices. 6. Work with communication standards such as RS485 and I2C for system integration. 7. Debug and troubleshoot FPGA designs using appropriate tools and methodologies. 8. Collaborate with cross-functional teams to ensure system-level integration and performance. 9. Document design processes, test procedures, and results for future reference. Good to have Skills: 1. Experience with additional FPGA platforms or programming languages. 2. Knowledge of advanced debugging tools and methodologies. 3. Exposure to high-speed communication protocols. Soft Skills: 1. Solid problem-solving skills and attention to detail. 2. Excellent communication and teamwork abilities.

Job Title: Senior Manager / Assistant General Manager - Synthesis (API) Department: Synthesis Location: Dholka , Ahmedabad - Gujarat Contact Person : Sharad Yadav ( HR ) - 6354520051 Required Qualifications & Experience: Ph.D./M.Sc. in Organic Chemistry or a related field. 12 -18 years of relevant experience in API synthesis and process development. Hands-on experience in route scouting, process optimization, impurity profiling, and scale-up. Familiar with regulatory guidelines (ICH, USFDA, EMA). Experience in handling QbD-based development is a plus. Key Competencies: Strong knowledge of organic synthesis and reaction mechanisms. Excellent leadership and team management skills. Good understanding of GMP/GLP and regulatory documentation. Analytical thinking, problem-solving, and decision-making abilities. Strong communication and interpersonal skills.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description Create System and FPGA designs to exercise all the use models targeted for each product mimicking end applications in a customer setting. Write system and product level validation plans for new and existing silicon products and projects; execute per plan, record and communicate results FPGA prototyping and emulation. Understanding spec., writing emulation plan and executing per plan. Record and communicate results. Understand hardware architectures, use models and system level design implementations required to utilize the silicon features. Be an effective contributor in a cross-functional team-oriented environment. Write high quality code in Verilog, VHDL and C code for embedded processors. Maintain existing code. Learn new system designs and validation methodologies. Understand FPGA architectures. o Be conversant with on-chip debug tool Requirements/Qualifications Qualifications/Requirements Excellent verbal and written communication skills in English 2+ Years experience in Design with RTL coding in Verilog and VHDL and Verification of RTL Possess an in-depth understanding of hardware architectures, system level IC design implementation, knowledge of how to create end use scenarios Optimizing code for FPGA architectures Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Basic knowledge of embedded processors such as ARM Cortex-M3 or RISC and familiarity with AMBA protocols APB, AHB, AXI, ACE Working knowledge on embedded software C/C++ is also a plus Strong technical background in FPGA prototype emulation, and debug Strong technical background in silicon validation, failure analysis and debug Excellent Board level debug capabilities in lab environment : hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Idenitfy, Xilinx Chipscope, Altera Signalscope, Lattice Reveal Design with RTL coding in Verilog and VHDL is a must Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools Hands-on systems level design and debug experience with at least two of the following high-speed serial communications protocols: i. PCIe Gen1/2/3 ii. Interlaken (10.3125 Gbps) iii. CPRI (614.4Mbps – 12.672 Gbps) iv. SGMII or QSGMII v. XAUI or HiGig/+/II vi. 10GBASE-R/-KR vii. Serial Rapid IO Travel Time 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

Job Title: Physical Design Engineer Company: Wipro Domain: Semiconductor | VLSI | Chip Design Experience: 7 to 15 Years Location: Bangalore / Hyderabad / Cochin / Pune Budget: ₹30 LPA to ₹75 LPA Work Mode: 5 Days Office Key Responsibilities: End-to-end ownership of chip-level and block-level floor planning . Drive partitioning, placement, clock tree synthesis (CTS), and routing. Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation. Perform timing analysis , DRC/LVS closure , and physical verification. Collaborate with cross-functional teams including RTL, DFT, STA, and packaging teams. Key Skills Required: Strong experience in chip-level and block-level physical design . Hands-on expertise with Innovus and/or Fusion Compiler . Solid understanding of timing, power, signal integrity, and physical verification. Exposure to advanced technology nodes (e.g., 7nm, 5nm) is a plus. Excellent problem-solving and debugging skills. Interview Process: L1 Technical Round – Virtual L2 Final Round – Virtual Job Types: Full-time, Permanent Pay: ₹3,000,000.00 - ₹7,500,000.00 per year Schedule: Monday to Friday Ability to commute/relocate: Pune, Maharashtra: Reliably commute or planning to relocate before starting work (Preferred) Application Question(s): End-to-end ownership of chip-level and block-level floor planning? Utilize tools like Cadence Innovus and Synopsys Fusion Compiler for implementation? Perform timing analysis, DRC/LVS closure, and physical verification? Work Location: In person

Note: Candidates refrain from re-applying if applied before : This is not a routine internship — only apply if you're ready to work hard, think independently, and solve real scientific challenges without hand-holding. Only fearless minds with real passion for electrochemical/Material innovation should apply — this is no place for comfort-seekers or resume-fillers . Not a Routine Role! This position is designed for scientists who seek deep innovation, value hard scientific problem-solving, and want to build something that has never existed in India. You’ll be part of a lean, focused team working at the frontier of technology — where there is no instruction manual, only initiative, creativity, and relentless experimentation. About Aryo Green Tech Pvt. Ltd. Aryo Green Tech Pvt. Ltd., a startup incubated in the Ideation Innovation & Incubation (I-3) Foundation (I3F, IIT BHU) incubation center, We have also collaboration with CSIR-CECRI , so that we are at the forefront of Aluminum-ion battery (AIB) innovation. In collaboration with industry leaders like Indian Oil Corporation Limited (IOCL) , we are revolutionizing the energy storage sector with sustainable, high-performance solutions. Aryo Green Tech is building India’s next-generation Aluminium-ion battery platform — safe, recyclable, and truly indigenous. From synthesizing novel materials to full-stack battery development, we’re creating high-performance alternatives to lithium-based systems. This is more than a job — it’s a scientific mission to build India’s energy future, free from dependency and compromise. Full-time Placement (based on Results & Work Performance) Start Date: Immediate Eligibility: PhD holders only with hands-on battery research background Stipend : Negotiable Materials Development: Design and optimize high-performance cathode and anode materials, including high-entropy metal oxides, metal alloys, and composites. Utilize advanced synthesis techniques (organic and inorganic) and other modification strategies to enhance material properties. Electrolyte Engineering: Develop innovative aqueous and ionic liquid electrolytes with exceptional ionic conductivity and electrochemical stability. Explore Gel-Polymer, Eutectic & non-aqueous electrolyte formulations to improve safety and performance. Focus on SEI layer stabilization, dendrite suppression, and electrolyte-component compatibility. Cell Design and Fabrication: Design and fabricate coin, pouch, cylindrical, and prismatic AIB cells for rigorous testing. Develop scalable and reproducible cell assembly protocols to support commercialization. Performance Optimization and Testing: Conduct advanced electrochemical testing (CV, galvanostatic cycling, EIS) to evaluate energy density, power density, cycle life, and thermal stability. Perform in-depth failure analysis to identify root causes and optimize battery performance. Advanced Characterization: Utilize cutting-edge techniques (e.g. XRD, SEM, FTIR) to analyze materials, electrolytes, and interfacial interactions. Investigate degradation mechanisms to improve battery longevity and reliability. Nutshell: You will join our core battery development team and contribute to: Synthesis and engineering of advanced electrode/electrolyte materials Assembly and optimization of Al-ion coin/pouch cells (aqueous & non-aqueous) Performance tuning for specific capacity, reversibility, and stability Material & electrochemical characterization: CV, EIS, XRD, SEM, BET Contribution to lab documentation, IP filings, and possible publications Who Should apply: We are looking for PhD-qualified candidates with strong foundations in: Electrochemistry, Material Science, Energy Storage, Nanotechnology, or Solid-State Chemistry Prior hands-on experience in battery R&D — Zn-ion, Na-ion, Al-ion, or related systems Skills in lab synthesis techniques (e.g., sol-gel, Solid-State, co-precipitation) Familiarity with battery fabrication tools and electrochemical instruments 🏆 What You Get Opportunity to work on India’s first serious Aluminium-ion battery initiative Total immersion in cutting-edge energy storage R&D Mentorship from founders and leading electrochemists Chance for full-time placement as part of the founding scientific team A legacy role in a bold national-tech mission How to Apply: Apply via LinkedIn or email your resume @ 📩 To Apply Email your CV + 5-line SOP (Why you want to build Aluminium-ion batteries) to: 📧 hr @aryogreentech.com Subject: for Application – R&D Scientist Internship-cum-placement (Al-ion Battery – PhD Only) Stipend : Negotiable based on expertise and experience Let's shape the future of energy storage together! Thanks for being a part of this beautiful R&D journey!

Key Responsibilities: Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability. Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area). Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization. Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization. Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design. Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic. RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies. Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met. Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues. Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference. Qualifications: Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree. Experience: Minimum 3-14 years of experience in ASIC physical design. Proficiency in place and route (P&R), static timing analysis (STA), power analysis , and DRC/LVS checks. Experience with tools like Cadence Innovus , Synopsys IC Compiler , or Mentor Graphics for physical design. Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus. Technical Skills: Proficiency in digital design concepts and semiconductor process flows. Strong knowledge of timing optimization techniques and power optimization strategies. Familiarity with parasitic extraction and signal integrity analysis. Ability to script in languages like Tcl , Python , or Perl to automate tasks. Preferred Skills: Experience with 3D IC design or FinFET technologies. Familiarity with full-chip tape-out procedures. Exposure to machine learning techniques in physical design optimization will be added advantage.

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. To be part of a highly skilled and challenging high speed parallel PHY such as DDR, LPDDR etc design team. Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc Responsible for various aspects of design and verification from spec to silicon along with interface design for controller and SoC. Active involvement in problem solving and implementing opportunities for improvement Mentoring and coaching other design team members on technical issues Pair with Analog designers to ensure smooth interface between Digital and Analog circuits Equal opportunity position with excellent pay package! SKILLS Required Strong fundamental knowledge of digital design, Verilog and scripting languages Experience with micro-architecture and Asynchronous digital designs Working knowledge of Synthesis, STA, Lint & CDC Working knowledge of DDR/LPDDR JEDEC protocol and DDR PHY designs Experience with DDR training algorithms and data path designs Experience in domain transfer designs, APB/JTAG, DFI M.S./M.Tech, BS/BE (Electronics) About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

Location: Singapore or India. The Regional APAC CP Manufacturing Leader is accountable for safe, reliable, and cost competitive operation of all internal and external Synthesis and F&P assets within the region. These assets have a strong focus on quality and agility to reliably serve customers. The Regional APAC CP Manufacturing Leader works closely with internal site leaders & external manufacturing leaders to ensure that resources are available to enable a high level of EHS&S, Quality and operational excellence as well as to enable talent development for the region. Key Responsibilities Set expectations and ensure alignment for regional Synthesis and F&P teams in relation to EH&S, Quality, Supply, Productivity, People, Cost Management, etc. Ensure metrics are in place to track and communicate performance. Provide input for 0-2 yr manufacturing cost forecast and performance, for both fixed and variable costs (considering idle mills, project expenses, plant inventory write-offs) Accountable for spend v plan for both internal and external manufacturing, forecast 0-2 yrs (including fixed, variable, recipe, BOM, routing) Accountable for internal site full compliance with all regulatory requirements and/or Corteva requirements (EHS&S, Quality, Equipment Reliability) Accountable for external manufacturing performance (EHS&S, Quality, Equipment Reliability) and regulatory compliance. Ensure EHSQ audits are completed at least every 5 years, and any gaps/findings from these audits are closed in timely manner. Provide input on supply strategy for both internal & external manufacturing in the region through the BRP process to increase competitive advantage in short-, medium-, and long-term time horizons, including input on regional strategic EM suppliers to include in the SRM program. Execute supply strategy and BRP (on time/on cost) accordingly by translating its needs into site/EM goals, activities and KPIs. Regular follow up with Site Leaders/EM Production Leaders to understand issues and eliminate roadblocks for implementation Ensure delivery of production plans. Awareness of EH&S, Quality, Supply or other significant issues at internal sites and EM partners, ensure business is informed (and keep updated on progress), ensure resources (both within function and cross-functionally) are available and collaborating effectively to appropriately mitigate impact of issue and ensure re-occurrence is eliminated (via RCIs as necessary) Ensure Site Leaders/EM Production Leaders aligned to expectation of preventing serious/significant EHS&S and Quality events at both internal/EM sites, as well as makes resources available to address key issues Actively track costs for internal sites & external manufacturing, and work closely with Site Leaders/EM Leaders to identify improvement opportunities to reduce conversion costs at internal sites and spend at external manufacturing partners respectively Develop annual goals & objectives, and performance targets for regional F&P and EM Synthesis teams, in alignment with business needs. Ensure alignment of goals & objectives at internal sites/EM’s. Ensure regional teams completion goals & objectives and achievement of performance targets. Take action to address any issues that prevent achievement of these activities. Work with Regional F&P Technology organization and EM TA to ensure BRP is followed at internal and external sites, Asset Resource Plans (ARP) developed which address gaps or opportunities for legal & compliance (L&C), run & maintain, growth & improvement and productivity. Ensure alignment of ARP’s with BRP needs. Prioritize plans and obtain support for CAPEX/non-capital funds to execute ARP’s Practice balanced people leadership (Employee Development Plans/Succession Planning/OHI/Morale). Promote & support employee development with focus on top talent within regional organization Additional Responsibilities Identify strategic improvement opportunities for the business, obtain support to proceed from executive leadership, and progress implementation to realize benefits to business. Represent Operations in the Regional F&P Strategy Team and in the Regional SRM process Leads the Performance process for the regional internal and external plants The Regional APAC CP Manufacturing Leader partners with the following team members closely: the Regional Supply Chain Leader (RSCL) to ensure F&P supply plans are being met and risks are proactively managed to deliver on customer needs the Partner Relationship Leader to ensure the EM Synthesis supply plans and risks are managed according to the Supplier Relationship Management process the Regional Technology Leader (RTL) and the External Manufacturing Technology Advisor (EM TA) to ensure technology and capital are available to deliver on the ARP (Area Relationship Plans) in alignment with the BRP. the Regional F&P Strategy Steering Team (RFPSST) for launch of new formulations and execution of supply resiliency plans the Central Group Leaders and Experts to ensure Technology, Safety, Process Safety and Quality Requirements for internal & external sites are being met, provide support for Quality issues and/or improvement initiatives, and coordinate auditing plans for internal & external sites RAPID/RACI Responsibilities Agree short term manufacturing strategy and capacity consumption targets/profiles (RCCP) Agree what facilities and resources are required to execute the ARPs (personnel, training and onboarding, site logistics, maintenance, waste, improvements, etc) Communicate EHS&S/Quality related incidents and their ongoing progress to IOLT and other stakeholders as relevant Timely communicate constraints or threats to weekly and monthly production plans to IOLT and other relevant stakeholders Communicate regional allocations (i.e., actives, co-formulants, or packaging constraints) to relevant stakeholders Communicate to region CU leaders any F&P plant shutdowns, logistics disruptions, natural disasters, quality issues, etc impacting Corteva business Education And Job Experience Requirements BS in Engineering or equivalent 15 years of Chemical Manufacturing Experience Site Leadership Process Safety & Health & Safety Knowledge People Leadership

Industry & Sector We are a rapidly scaling player in the global Digital Publishing & EdTech sector, delivering expertly crafted educational content to universities, K-12 platforms, and lifelong learners worldwide. Our multidisciplinary teams turn scholarly expertise into engaging multimedia learning experiences, distributed across web, mobile, and print channels. Operating fully remote, we prize intellectual rigor, creative flair, and data-driven decision making. Role: Content Writer – Literature Specialist Role & Responsibilities Create research-backed articles, study guides, and marketing assets on classic and contemporary English literature that meet C1 linguistic standards and in-house SEO guidelines. Perform deep textual analysis, comparative criticism, and secondary-source synthesis to generate original, plagiarism-free copy suitable for academic and popular audiences. Own end-to-end content lifecycle—ideation, outline, drafting, peer review, revision, and CMS publication—while meeting weekly throughput targets. Collaborate with editors, instructional designers, and growth marketers to align tone, pedagogy, and keyword strategy. Maintain rigorous citation integrity using MLA/APA/Chicago styles and ensure compliance with anti-plagiarism tooling. Coach junior writers and subject-matter freelancers, sharing best practices in narrative flow, voice consistency, and fact-checking. Skills & Qualifications Must-Have Ph.D. in English Literature or related humanities discipline. Native-level or certified C1 English proficiency with demonstrable publication record. 3+ years professional content writing or academic publishing experience. Expertise in close reading, critical theory, and genre-specific stylistics. Hands-on SEO keyword research, on-page optimization, and content analytics tools (Surfer, SEMrush, Google Analytics). Mastery of MS Office or Google Workspace and at least one CMS (WordPress, Contentful, or similar). Preferred Experience developing MOOCs or e-learning modules. Familiarity with AI-assisted writing and version control workflows (Git). Benefits & Culture Highlights 100% remote, flexible hours with asynchronous collaboration. Annual learning stipend for conferences, journals, and upskilling. Peer community of scholars, writers, and technologists who value autonomy and impact. Skills: literature,content analytics tools,critical theory,academic writing,c1 english proficiency,on-page optimization,academic publishing,curriculum design,seo copywriting,ph.d. in english literature or related humanities discipline,google workspace,close reading,seo keyword research,content writing,english literature,english,ms office,genre-specific stylistics,cms (wordpress, contentful or similar)